From 38a81e840e228d789c34262de5623c1c6c269190 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 20 Mar 2022 10:29:27 +0800 Subject: [PATCH] [Script] Skip analysis SDC in multi-clock benchmarks --- .../global_tile_multiclock_example_script.openfpga | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index 1b1daae4d..97e679445 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -72,7 +72,9 @@ write_pnr_sdc --file ./SDC write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +# TODO: Currently analysis SDC does not support multiple clocks due to +# - Missing information about which I/Os are constrained by which clock +#write_analysis_sdc --file ./SDC_analysis # Finish and exit OpenFPGA exit