riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Patch task configuration file for lut_adder_test to use correct rewrite script

This commit is contained in:
tangxifan 2021-03-08 21:38:51 -07:00
parent c53c41b7a5
commit 37aa42d305
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
View File

@ -30,8 +30,9 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench1_top = adder_8
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
##########################