From 37aa42d305e5dfe84e7b5db6748520520c5750d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Mar 2021 21:38:51 -0700 Subject: [PATCH] [Test] Patch task configuration file for lut_adder_test to use correct rewrite script --- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 6f711649b..8f69e98b6 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -30,8 +30,9 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys + bench1_top = adder_8 -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] ##########################