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simplify the local wire generation for ccffs

This commit is contained in:
tangxifan 2019-09-28 21:36:56 -06:00
parent 1983e56557
commit 3726e691f4
3 changed files with 65 additions and 49 deletions
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9
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -340,8 +340,6 @@ std::string generate_mux_local_decoder_addr_port_name() {
return std::string("addr"); return std::string("addr");
} }
/********************************************************************* /*********************************************************************
* Generate the data port (output) for a local decoder of a multiplexer * Generate the data port (output) for a local decoder of a multiplexer
* TODO: This could be replaced as a constexpr string * TODO: This could be replaced as a constexpr string
@ -358,6 +356,13 @@ std::string generate_mux_local_decoder_data_inv_port_name() {
return std::string("data_inv"); return std::string("data_inv");
} }
/*********************************************************************
* Generate the port name of a local configuration bus
* TODO: This could be replaced as a constexpr string
*********************************************************************/
std::string generate_local_config_bus_port_name() {
return std::string("config_bus");
}
/********************************************************************* /*********************************************************************
* Generate the port name for a regular sram port which appears in the * Generate the port name for a regular sram port which appears in the

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
View File

@ -82,6 +82,8 @@ std::string generate_mux_local_decoder_data_port_name();
std::string generate_mux_local_decoder_data_inv_port_name(); std::string generate_mux_local_decoder_data_inv_port_name();
std::string generate_local_config_bus_port_name();
std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model, const CircuitModelId& sram_model,
const e_sram_orgz& sram_orgz_type, const e_sram_orgz& sram_orgz_type,

93
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -651,7 +651,8 @@ void print_verilog_buffer_instance(std::fstream& fp,
/******************************************************************** /********************************************************************
* Print local wires that are used for SRAM configuration * Print local wires that are used for SRAM configuration
* The local wires are strongly dependent on the organization of SRAMs. * The local wires are strongly dependent on the organization of SRAMs.
* 1. Standalone SRAMs: * Standalone SRAMs:
* -----------------
* No need for local wires, their outputs are port of the module * No need for local wires, their outputs are port of the module
* *
* Module * Module
@ -665,36 +666,61 @@ void print_verilog_buffer_instance(std::fstream& fp,
* | +---------------------+ | * | +---------------------+ |
* +------------------------------+ * +------------------------------+
* *
* 2. Configuration-chain Flip-flops: * Configuration chain-style
* two ports will be added, which are the head of scan-chain * -------------------------
* and the tail of scan-chain * wire [0:N] config_bus
*
* *
* Module * Module
* +-----------------------------------------+ * +--------------------------------------------------------------+
* | config_bus config_bus config_bus config_bus |
* | [0] [1] [2] [N] |
* | | | | | |
* | v v v v |
* ccff_head| ----------+ +---------+ +------------+ +----------------|-> ccff_tail
* | | ^ | ^ | ^ |
* | head v |tail v | v | |
* | +----------+ +----------+ +----------+ |
* | | Memory | | Memory | | Memory | |
* | | Module | | Module | ... | Module | |
* | | [0] | | [1] | | [N] | |
* | +----------+ +----------+ +----------+ |
* | | | | |
* | v v v |
* | +----------+ +----------+ +----------+ |
* | | MUX | | MUX | | MUX | |
* | | Module | | Module | ... | Module | |
* | | [0] | | [1] | | [N] | |
* | +----------+ +----------+ +----------+ |
* | | * | |
* | +------+ +------+ +------+ | * +--------------------------------------------------------------+
* | +->| CCFF |--->| CCFF | ... | CCFF |-+ | *
* | | +------+ | +------+ | +------+ | | * Memory bank-style
* head--->|-+-----------+------------+-----------+->|--->tail * -----------------
* | local wire |
* +-----------------------------------------+
* 3. Memory decoders:
* two ports will be added, which are regular output and inverted output * two ports will be added, which are regular output and inverted output
* Note that the outputs are the data outputs of SRAMs * Note that the outputs are the data outputs of SRAMs
* BL/WLs of memory decoders are ports of module but not local wires * BL/WLs of memory decoders are ports of module but not local wires
* *
* Module * Module
* +-----------------------------------------+ * +-------------------------------------------------+
* | | * | |
* | +------+ +------+ +------+ | BL/WL bus --+--------+------------+-----------------+ |
* | | SRAM | | SRAM | ... | SRAM | |
* | +------+ +------+ +------+ |
* | ^ ^ ^ |
* | | | | | * | | | | |
* BL/WL--->|---------------------------------------->| * | BL/WL v BL/WL v BL/WL v |
* | local wire | * | +----------+ +----------+ +----------+ |
* +-----------------------------------------+ * | | Memory | | Memory | | Memory | |
* | | Module | | Module | ... | Module | |
* | | [0] | | [1] | | [N] | |
* | +----------+ +----------+ +----------+ |
* | | | | |
* | v v v |
* | +----------+ +----------+ +----------+ |
* | | MUX | | MUX | | MUX | |
* | | Module | | Module | ... | Module | |
* | | [0] | | [1] | | [N] | |
* | +----------+ +----------+ +----------+ |
* | |
* +-------------------------------------------------+
* *
********************************************************************/ ********************************************************************/
void print_verilog_local_sram_wires(std::fstream& fp, void print_verilog_local_sram_wires(std::fstream& fp,
@ -717,36 +743,19 @@ void print_verilog_local_sram_wires(std::fstream& fp,
break; break;
case SPICE_SRAM_SCAN_CHAIN: { case SPICE_SRAM_SCAN_CHAIN: {
/* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */ /* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */
std::vector<BasicPort> ccff_ports;
/* [0] => CCFF input */ /* [0] => CCFF input */
ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), port_size)); BasicPort ccff_config_bus_port(generate_local_config_bus_port_name(), port_size);
/* [1] => CCFF output */ fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl;
ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), port_size));
/* [2] => CCFF inverted output */
ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INOUT), port_size));
/* Print local wire definition */
for (const auto& ccff_port : ccff_ports) {
fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_port) << ";" << std::endl;
}
/* Connect first CCFF to the head */ /* Connect first CCFF to the head */
/* Head is always a 1-bit port */ /* Head is always a 1-bit port */
BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1);
BasicPort ccff_head_local_port(ccff_ports[0].get_name(), 1); BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1);
print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false);
/* Connect last CCFF to the tail */ /* Connect last CCFF to the tail */
/* Tail is always a 1-bit port */ /* Tail is always a 1-bit port */
BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1);
BasicPort ccff_tail_local_port(ccff_ports[1].get_name(), ccff_ports[1].get_msb(), ccff_ports[1].get_msb()); BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb());
print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false);
/* Connect CCFFs into chains */
/* If port size is 0 or 1, there is no need for the chain connection */
if (2 > port_size) {
break;
}
/* Cascade the CCFF between head and tail */
BasicPort ccff_chain_input_port(ccff_ports[0].get_name(), port_size - 1);
BasicPort ccff_chain_output_port(ccff_ports[1].get_name(), 1, port_size - 1);
print_verilog_wire_connection(fp, ccff_chain_output_port, ccff_chain_input_port, false);
break; break;
} }
case SPICE_SRAM_MEMORY_BANK: { case SPICE_SRAM_MEMORY_BANK: {