removed the -nolatches option in run_fpga_flow script
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@ -489,7 +489,8 @@ def create_yosys_params():
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if not args.verific:
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ys_params["READ_VERILOG_FILE"] = " \n".join([
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"read_verilog -nolatches " + shlex.quote(eachfile)
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#"read_verilog -nolatches " + shlex.quote(eachfile)
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"read_verilog " + shlex.quote(eachfile)
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for eachfile in args.benchmark_files])
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else:
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if "ADD_INCLUDE_DIR" not in ys_params:
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