diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 08e33b0c7..bb44f2f40 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -489,7 +489,8 @@ def create_yosys_params():
 
     if not args.verific:
         ys_params["READ_VERILOG_FILE"] = " \n".join([
-            "read_verilog -nolatches " + shlex.quote(eachfile)
+            #"read_verilog -nolatches " + shlex.quote(eachfile)
+            "read_verilog " + shlex.quote(eachfile)
             for eachfile in args.benchmark_files])
     else:
         if "ADD_INCLUDE_DIR" not in ys_params: