Adding decoder task
This commit is contained in:
CHARAS SAMY
parent
85bbed1b1f
commit
35fccf2214
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INV_X1N_A9PP84TR_C14" prefix="INV_X1N_A9PP84TR_C14" is_default="true" verilog_netlist="/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/std_cell/Verilog/std_cell_extract_timing_BA.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="BUF_X4N_A9PP84TR_C14" prefix="BUF_X4N_A9PP84TR_C14" verilog_netlist="/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/std_cell/Verilog/std_cell_extract_timing_BA.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV_X4N_A9PP84TR_C14" prefix="INV_X4N_A9PP84TR_C14" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV_X2N_A9PP84TR_C14" prefix="INV_X2N_A9PP84TR_C14" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="BUF_X2N_A9PP84TR_C14" prefix="BUF_X2N_A9PP84TR_C14" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="BUF_X1N_A9PP84TR_C14" prefix="BUF_X1N_A9PP84TR_C14" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="MX2_X1N_A9PP84TR_C14" prefix="MX2_X1N_A9PP84TR_C14" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="MUX2"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="B" size="1"/>
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<port type="input" prefix="b" lib_name="A" size="1"/>
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<port type="input" prefix="s" lib_name="S0" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="gate" name="OR2_X1N_A9PP84TR_C14" prefix="OR2_X1N_A9PP84TR_C14" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos" topology="OR"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_like" prefix="mux_tree_like" dump_structural_verilog="true" is_default="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<pass_gate_logic circuit_model_name="MX2_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_like_tapbuf" prefix="mux_tree_like_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X4N_A9PP84TR_C14"/>
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<pass_gate_logic circuit_model_name="MX2_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="SDFFRPQ_X1N_A9PP84TR_C14" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_spice/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="D" lib_name="D" size="1"/>
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<port type="input" prefix="D_chain" lib_name="SI" size="1"/>
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<port type="input" prefix="Reset" lib_name="R" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
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<port type="output" prefix="Q" lib_name="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<lut_input_inverter exist="true" circuit_model_name="INV_X2N_A9PP84TR_C14"/>
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<lut_input_buffer exist="true" circuit_model_name="BUF_X1N_A9PP84TR_C14"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="BUF_X1N_A9PP84TR_C14" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="MX2_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2_X1N_A9PP84TR_C14"/>
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="CCFFX1" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="CCFFX1" prefix="ccff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_spice/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="pReset" lib_name="R" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" lib_name="D" size="1"/>
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<port type="output" prefix="Q" lib_name="Q" size="1"/>
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<port type="output" prefix="Qb" lib_name="QB" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_spice/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<!-- RTO and SNSsignals are not a part of FPGA core now -->
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<port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" />
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<port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true" />
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<port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true" />
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<port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true" />
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<port type="sram" prefix="en" lib_name="mem_out" size="1" mode_select="true" circuit_model_name="CCFFX1" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="in" size="1"/>
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<port type="output" prefix="inpad" lib_name="out" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="ADDF_X1N_A9PP84TR_C14" prefix="ADDF_X1N_A9PP84TR_C14" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/sc_verilog/std_cell_extract.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<output_buffer exist="true" circuit_model_name="INV_X1N_A9PP84TR_C14"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="input" prefix="cin" lib_name="CI" size="1"/>
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<port type="output" prefix="sumout" lib_name="S" size="1"/>
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<port type="output" prefix="cout" lib_name="CO" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="CCFFX1"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_tree_like_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_tree_like_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="adder_carry" circuit_model_name="direct_interc"/>
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<direct name="scff_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
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<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFRPQ_X1N_A9PP84TR_C14"/>
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<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="ADDF_X1N_A9PP84TR_C14"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'n2_lut5' -->
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:4]"/>
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<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
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<!-- Binding operating pb_types in mode 'arithmetic' -->
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].frac_logic.adder_phy"/>
|
||||
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
|
||||
<!-- Binding operating pb_types in mode 'ble6' -->
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="00">
|
||||
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:5]"/>
|
||||
<port name="out" physical_mode_port="lut6_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
|
||||
<!-- Binding operating pb_types in mode 'shift_register' -->
|
||||
<pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
|
||||
<!-- End physical pb_type binding in complex block CLB -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
<openfpga_simulation_setting>
|
||||
<clock_setting>
|
||||
<!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
|
||||
<operating frequency="200e6" num_cycles="auto" slack="0.2"/>
|
||||
<programming frequency="10e6"/>
|
||||
</clock_setting>
|
||||
<simulator_option>
|
||||
<operating_condition temperature="25"/>
|
||||
<output_log verbose="false" captab="false"/>
|
||||
<accuracy type="abs" value="1e-13"/>
|
||||
<runtime fast_simulation="true"/>
|
||||
</simulator_option>
|
||||
<monte_carlo num_simulation_points="2"/>
|
||||
<measurement_setting>
|
||||
<slew>
|
||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
||||
</slew>
|
||||
<delay>
|
||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||
</delay>
|
||||
</measurement_setting>
|
||||
<stimulus>
|
||||
<clock>
|
||||
<rise slew_type="abs" slew_time="20e-12" />
|
||||
<fall slew_type="abs" slew_time="20e-12" />
|
||||
</clock>
|
||||
<input>
|
||||
<rise slew_type="abs" slew_time="25e-12" />
|
||||
<fall slew_type="abs" slew_time="25e-12" />
|
||||
</input>
|
||||
</stimulus>
|
||||
</openfpga_simulation_setting>
|
||||
|
|
@ -0,0 +1,682 @@
|
|||
<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
|
||||
|
||||
- The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
|
||||
surrounded by a ring of I/Os
|
||||
- [TODO] Delay numbers are extracted from a 12 nm technology
|
||||
Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<model name="adder">
|
||||
<input_ports>
|
||||
<port name="a" combinational_sink_ports="sumout cout"/>
|
||||
<port name="b" combinational_sink_ports="sumout cout"/>
|
||||
<port name="cin" combinational_sink_ports="sumout cout"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="cout"/>
|
||||
<port name="sumout"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="frac_lut6">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut4_out"/>
|
||||
<port name="lut5_out"/>
|
||||
<port name="lut6_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="shift">
|
||||
<input_ports>
|
||||
<port name="D" clock="clk"/>
|
||||
<port name="clk" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="clk"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="scff">
|
||||
<input_ports>
|
||||
<port name="D" clock="clk"/>
|
||||
<port name="D_chain" clock="clk"/>
|
||||
<port name="clk" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="clk"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<!-- Each I/O tile includes a GPIO -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<tile name="io" capacity="1" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<!-- Each input of the tile can be driven by 15% of routing tracks
|
||||
Each output of the tile can drive 10% of routing tracks
|
||||
-->
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<!-- Each CLB tile includes a Configurable Logic Block (CLB)
|
||||
Each input of the tile can be driven by 15% of routing tracks
|
||||
Each output of the tile can drive 10% of routing tracks
|
||||
-->
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I0" num_pins="10" equivalent="full"/>
|
||||
<input name="I1" num_pins="10" equivalent="full"/>
|
||||
<input name="I2" num_pins="10" equivalent="full"/>
|
||||
<input name="I3" num_pins="10" equivalent="full"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="cin_trick" num_pins="1"/>
|
||||
<input name="regin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="cout_copy" num_pins="1"/>
|
||||
<output name="regout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Each input of the tile can be driven by 15% of routing tracks
|
||||
Each output of the tile can drive 10% of routing tracks
|
||||
There are four pins (cin, cout, sc_in, sc_out) has not connection
|
||||
to routing tracks. There are directed wired from/to adjacent CLBs
|
||||
-->
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
|
||||
<!-- To ensure best tileable routing architecture (minimize the number of unique SBs
|
||||
We keep all the pins that touch routing architecture on the right and bottom sides of the tile
|
||||
Top side pins are mainly for direct connections
|
||||
-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left"></loc>
|
||||
<loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
|
||||
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
|
||||
<loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<!-- Apply tileable routing architecture.
|
||||
This is strongly recommended if you want to PnR large FPGA fabric
|
||||
-->
|
||||
<layout tileable="true">
|
||||
<!--auto_layout aspect_ratio="1.0"-->
|
||||
<!-- Apply a fixed layout of 2x2 core array.
|
||||
VPR8 considers the I/O ring in the array size
|
||||
Therefore the height and width are both 4
|
||||
-->
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<!-- /auto_layout -->
|
||||
</layout>
|
||||
<device>
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<!-- Use Wilton-style connecting pattern in switch block
|
||||
Each routing track has access to only three other routing tracks
|
||||
(one per each side of the switch block except the side where the routing track locates)
|
||||
-->
|
||||
<switch_block type="wilton" fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<directlist>
|
||||
<!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
|
||||
<direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
<!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
|
||||
<direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
</directlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" packable="false">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define multi-mode Configurable Logic Block (CLB) begin -->
|
||||
<!-- Technical highlight:
|
||||
K6_frac_N10_I40_chain_shiftreg_depop50
|
||||
- K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
|
||||
which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs
|
||||
In addition to 6-LUT, each LE also includes two Flip-Flops
|
||||
- N10: every CLB consists of 10 LEs and a local routing architecture
|
||||
- I40: every CLB has 40 inputs
|
||||
- chain: a hard adder chain across all the LEs in a CLB
|
||||
The inputs of adder are driven by 4-LUTs.
|
||||
The sumout of adder can optional drive an LE output or a Flip-Flop
|
||||
The carry-out of adder will drive the carry-in of the next adder in the chain
|
||||
- shiftreg: Flip-flops inside CLB can be configured as shift registers.
|
||||
The organization is similar the hard adder chain except it is programmable
|
||||
- depop50: every local routing multiplexer accesses to 50% of the CLB inputs
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I0" num_pins="10" equivalent="full"/>
|
||||
<input name="I1" num_pins="10" equivalent="full"/>
|
||||
<input name="I2" num_pins="10" equivalent="full"/>
|
||||
<input name="I3" num_pins="10" equivalent="full"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="cin_trick" num_pins="1"/>
|
||||
<input name="regin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="cout_copy" num_pins="1"/>
|
||||
<output name="regout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
|
||||
<!-- Describe fracturable logic element -->
|
||||
<pb_type name="fle" num_pb="10">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="sc_in" num_pins="1"/>
|
||||
<input name="regin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sc_out" num_pins="1"/>
|
||||
<output name="regout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
|
||||
<!-- Describe physical mode begins -->
|
||||
<mode name="physical" packable="false">
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="regin" num_pins="1"/>
|
||||
<input name="regchain" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="lut5_out" num_pins="2"/>
|
||||
<output name="lut6_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sumout" num_pins="1"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
|
||||
<direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
|
||||
<direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
|
||||
<direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
|
||||
<direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
|
||||
<direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
|
||||
<direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
|
||||
<direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
|
||||
<mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
|
||||
</mux>
|
||||
<mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="D_chain" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
|
||||
<T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
|
||||
<direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
|
||||
<direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
|
||||
<direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
|
||||
<direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
|
||||
<direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
|
||||
<direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
|
||||
<direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
|
||||
<direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
|
||||
<direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
|
||||
<direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
|
||||
<direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
|
||||
<mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
|
||||
</mux>
|
||||
<mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
|
||||
</mux>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define physical mode begins -->
|
||||
<!-- Define n2_lut5 mode begins -->
|
||||
<mode name="n2_lut5" packable="true">
|
||||
<pb_type name="lut5inter" num_pb="1">
|
||||
<input name="in" num_pins="5"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ble5" num_pb="2">
|
||||
<input name="in" num_pins="5"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<mode name="blut5">
|
||||
<pb_type name="flut5" num_pb="1">
|
||||
<input name="in" num_pins="5"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Regular LUT mode -->
|
||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||
202e-12
|
||||
202e-12
|
||||
202e-12
|
||||
202e-12
|
||||
202e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="flut5.in" output="lut5.in"/>
|
||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="flut5.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="flut5.in"/>
|
||||
<direct name="direct2" input="ble5.clk" output="flut5.clk"/>
|
||||
<direct name="direct3" input="flut5.out" output="ble5.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="arithmetic">
|
||||
<pb_type name="arithmetic" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Special dual-LUT mode that drives adder only -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
180e-12
|
||||
180e-12
|
||||
180e-12
|
||||
180e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="adder" blif_model=".subckt adder" num_pb="1">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sumout" num_pins="1"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clock" input="arithmetic.clk" output="ff.clk"/>
|
||||
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
|
||||
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
|
||||
<direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
|
||||
</direct>
|
||||
<direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
|
||||
</direct>
|
||||
<direct name="add_to_ff" input="adder.sumout" output="ff.D">
|
||||
<pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="carry_in" input="arithmetic.cin" output="adder.cin">
|
||||
<pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
|
||||
</direct>
|
||||
<direct name="carry_out" input="adder.cout" output="arithmetic.cout">
|
||||
<pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
|
||||
</direct>
|
||||
<mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
|
||||
<delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
|
||||
<direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
|
||||
<!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
|
||||
</direct>
|
||||
<direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
|
||||
<!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
|
||||
</direct>
|
||||
<direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
|
||||
<direct name="direct3" input="arithmetic.out" output="ble5.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
||||
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
||||
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
||||
<direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
|
||||
<!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
|
||||
</direct>
|
||||
<direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
|
||||
<!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
|
||||
</direct>
|
||||
<direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
|
||||
<!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
|
||||
</direct>
|
||||
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
||||
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
||||
<direct name="carry_in" input="fle.cin" output="lut5inter.cin">
|
||||
<!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
|
||||
</direct>
|
||||
<direct name="carry_out" input="lut5inter.cout" output="fle.cout">
|
||||
<!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define n2_lut5 mode ends -->
|
||||
<mode name="n1_lut6">
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||
229e-12
|
||||
229e-12
|
||||
229e-12
|
||||
229e-12
|
||||
229e-12
|
||||
229e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define n1_lut6 mode ends -->
|
||||
<!-- Define shift register mode begins -->
|
||||
<mode name="shift_register">
|
||||
<pb_type name="ble_shift" num_pb="1">
|
||||
<input name="in" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="regout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
|
||||
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
|
||||
<!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
|
||||
</direct>
|
||||
<direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
|
||||
<direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
|
||||
<direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
|
||||
<complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.regin" output="ble_shift.in"/>
|
||||
<direct name="direct2" input="ble_shift.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
|
||||
<direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define shift_register mode end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="crossbar0" input="clb.I2 clb.I3 fle[4:0].out" output="fle[4:0].in[0]">
|
||||
<delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[4:0].in[0]" />
|
||||
<delay_constant max="190e-12" in_port="fle[4:0].out" out_port="fle[4:0].in[0]" />
|
||||
</complete>
|
||||
<complete name="crossbar1" input="clb.I1 clb.I2 fle[4:0].out" output="fle[4:0].in[1]">
|
||||
<delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[4:0].in[1]" />
|
||||
<delay_constant max="190e-12" in_port="fle[4:0].out" out_port="fle[4:0].in[1]" />
|
||||
</complete>
|
||||
<complete name="crossbar2" input="clb.I0 clb.I1 fle[4:0].out" output="fle[4:0].in[2]">
|
||||
<delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[4:0].in[2]" />
|
||||
<delay_constant max="190e-12" in_port="fle[4:0].out" out_port="fle[4:0].in[2]" />
|
||||
</complete>
|
||||
<complete name="crossbar3" input="clb.I1 clb.I3 fle[4:0].out" output="fle[4:0].in[3]">
|
||||
<delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[4:0].in[3]" />
|
||||
<delay_constant max="190e-12" in_port="fle[4:0].out" out_port="fle[4:0].in[3]" />
|
||||
</complete>
|
||||
<complete name="crossbar4" input="clb.I0 clb.I2 fle[4:0].out" output="fle[4:0].in[4]">
|
||||
<delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[4:0].in[4]" />
|
||||
<delay_constant max="190e-12" in_port="fle[4:0].out" out_port="fle[4:0].in[4]" />
|
||||
</complete>
|
||||
<complete name="crossbar5" input="clb.I0 clb.I3 fle[4:0].out" output="fle[4:0].in[5]">
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[4:0].clk">
|
||||
</complete>
|
||||
<complete name="carry_in" input="clb.cin clb.cin_trick fle[4:0].out" output="fle[0:0].cin">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
|
||||
<pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
<!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
|
||||
</complete>
|
||||
|
||||
<!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
|
||||
<pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
</direct-->
|
||||
<direct name="clbouts1" input="fle[4:0].out[0:0]" output="clb.O[4:0]"/>
|
||||
<direct name="clbouts15" input="fle[9:5].out[0:0]" output="clb.O[9:5]"/>
|
||||
<direct name="clbouts2" input="fle[4:0].out[1:1]" output="clb.O[14:10]"/>
|
||||
<direct name="clbouts25" input="fle[9:5].out[1:1]" output="clb.O[19:15]"/>
|
||||
<direct name="cout_copy" input="fle[4:4].cout" output="clb.cout_copy"/>
|
||||
|
||||
<!-- Shift register links -->
|
||||
<direct name="regin" input="clb.regin" output="fle[0:0].regin">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
||||
<pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
|
||||
</direct>
|
||||
<direct name="regout" input="fle[4:4].regout" output="clb.regout">
|
||||
<pack_pattern name="chain" in_port="fle[4:4].regout" out_port="clb.regout"/>
|
||||
</direct>
|
||||
<direct name="reg_link" input="fle[3:0].regout" output="fle[4:1].regin">
|
||||
<pack_pattern name="chain" in_port="fle[3:0].regout" out_port="fle[4:1].regin"/>
|
||||
</direct>
|
||||
<!-- Carry chain links -->
|
||||
<direct name="carry_out" input="fle[4:4].cout" output="clb.cout">
|
||||
<pack_pattern name="chain" in_port="fle[4:4].cout" out_port="clb.cout"/>
|
||||
</direct>
|
||||
<direct name="carry_link" input="fle[3:0].cout" output="fle[4:1].cin">
|
||||
<pack_pattern name="chain" in_port="fle[3:0].cout" out_port="fle[4:1].cin"/>
|
||||
</direct>
|
||||
<!-- Scan chain links -->
|
||||
<direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
|
||||
</direct>
|
||||
<direct name="sc_out" input="fle[4:4].sc_out" output="clb.sc_out">
|
||||
</direct>
|
||||
<direct name="sc_link" input="fle[3:0].sc_out" output="fle[4:1].sc_in">
|
||||
</direct>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
#!/bin/bash
|
||||
wget –no-check-certificate -q -O - 'https://docs.google.com/spreadsheets/d/e/2PACX-1vQoLR2KbvU9BOF6PszjTtIrrY7nrb8GlHMlqC_VAjFgGrTF5ToGgPvfDRY-Pj0GjgamkaIglq7kTX7q/pub?gid=85930648&single=true&output=csv' > pin_map.csv
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,20 @@
|
|||
Left,,,,,,Right,,,,,,Top,,,,,,Bottom,,,,,,,,,,
|
||||
Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,,,,,
|
||||
1,7,1,DVSS,PDVSS_18_18_NT_DR,,2,7,1,DVSS,PDVSS_18_18_NT_DR,,3,7,1,DVSS,PDVSS_18_18_NT_DR,,4,7,1,DVSS,PDVSS_18_18_NT_DR,,Code,Name,Instance,Count,
|
||||
1,6,2,DVDD,PDVDD_18_18_NT_DR,,2,6,2,DVDD,PDVDD_18_18_NT_DR,,3,6,2,DVDD,PDVDD_18_18_NT_DR,,4,6,2,DVDD,PDVDD_18_18_NT_DR,,1,Global Port In,PINCNP_18_18_NT_DR,7,9
|
||||
1,1,3,Reset,PINCNP_18_18_NT_DR,,2,1,3,prog_clk,PINCNP_18_18_NT_DR,,3,1,3,sc_head,PINCNP_18_18_NT_DR,,4,1,3,ccff_head,PINCNP_18_18_NT_DR,,2,GPIO,PBIDIR_18_18_NT_DR,8,32
|
||||
1,2,4,GPIO1,PBIDIR_18_18_NT_DR,,2,2,4,GPIO4,PBIDIR_18_18_NT_DR,,3,2,4,GPIO7,PBIDIR_18_18_NT_DR,,4,2,4,GPIO2,PBIDIR_18_18_NT_DR,,3,SPY,PBIDIR_18_18_NT_DR,0,11
|
||||
1,1,5,clk,PINCNP_18_18_NT_DR,,2,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,3,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,4,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,4,VDD,PVDD_08_08_NT_DR,4,
|
||||
1,2,6,GPIO0,PBIDIR_18_18_NT_DR,,2,2,6,GPIO5,PBIDIR_18_18_NT_DR,,3,2,6,GPIO6,PBIDIR_18_18_NT_DR,,4,2,6,GPIO3,PBIDIR_18_18_NT_DR,,5,VSS,PVSS_08_08_NT_DR,4,
|
||||
1,1,7,Test_en,PINCNP_18_18_NT_DR,,2,1,7,pReset,PINCNP_18_18_NT_DR,,3,9,7,ccff_tail,PBIDIR_18_18_NT_DR,,4,9,7,sc_tail,PBIDIR_18_18_NT_DR,,6,DVDD,PDVDD_18_18_NT_DR,4,
|
||||
1,4,8,VDD,PVDD_08_08_NT_DR,,2,4,8,VDD,PVDD_08_08_NT_DR,,3,4,8,VDD,PVDD_08_08_NT_DR,,4,4,8,VDD,PVDD_08_08_NT_DR,,7,DVSS,PDVSS_18_18_NT_DR,4,
|
||||
1,5,9,VSS,PVSS_08_08_NT_DR,,2,5,9,VSS,PVSS_08_08_NT_DR,,3,5,9,VSS,PVSS_08_08_NT_DR,,4,5,9,VSS,PVSS_08_08_NT_DR,,8,PVDDTIE,PDVDDTIE_18_18_NT_DR,3,
|
||||
,,,,,,,,,,,,,,,,,,,,,,,,9,Global Port Out,PBIDIR_18_18_NT_DR,2,
|
||||
,,,,,,,,,,,,,,,,,,,,,,,,,,,36,
|
||||
,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
,,,,,,,,,,,,,,,,,,,,,,,,,,,,
|
||||
,,,,,,,,,,,,,,,,,,,,,,,,"Things to Edit
|
||||
1. Add respective numbers in the Pin column
|
||||
2. Add pin name in pi name column (case inensetive will be converted to lower case all the time)
|
||||
3. GPIO array is represented as GPIOxx
|
||||
4. Orientation will be taken care by the script",,,,
|
||||
|
|
|
@ -0,0 +1,34 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/run.openfpga
|
||||
openfpga_shell_template = /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/release/FROG_v1.0/SCRIPTS/openfpga_script_templates/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/arch/fpga22_openfpga_arch.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/arch/fpga22_vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = decoder_2_4
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.v
|
||||
#bench0_chan_width = 200
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
# end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,51 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Top-level Verilog module for FPGA
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
// Date: Wed Apr 22 16:46:21 2020
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- Verilog module for fpga_top -----
|
||||
module fpga_core(pReset,
|
||||
prog_clk,
|
||||
Reset,
|
||||
Test_en,
|
||||
clk,
|
||||
sc_head,
|
||||
sc_tail,
|
||||
gfpga_pad_GPIO_A,
|
||||
gfpga_pad_GPIO_IE,
|
||||
gfpga_pad_GPIO_OE,
|
||||
gfpga_pad_GPIO_Y,
|
||||
ccff_head,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] Reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] Test_en;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- GPOUT PORTS -----
|
||||
output [0:7] gfpga_pad_GPIO_A;
|
||||
//----- GPOUT PORTS -----
|
||||
output [0:7] gfpga_pad_GPIO_IE;
|
||||
//----- GPOUT PORTS -----
|
||||
output [0:7] gfpga_pad_GPIO_OE;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_Y;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
input [0:0]sc_head;
|
||||
output [0:0]sc_tail;
|
||||
//----- BEGIN wire-connection ports -----
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
# THis script creates top level wrapper for the FPGA Core
|
||||
# THe GPIo Pin assignement can be provided with csv file or
|
||||
# Link to google published sheet
|
||||
import veriloggen as vgen
|
||||
import pyverilog.utils.version
|
||||
import sys
|
||||
from pyverilog.vparser import ast
|
||||
from pyverilog.vparser.parser import parse
|
||||
import pandas as pd
|
||||
import os
|
||||
import re
|
||||
import shutil
|
||||
import argparse
|
||||
|
||||
|
||||
SIDE_MAP = ["", "left", "right", "top", "bottom"]
|
||||
|
||||
PIN_MAP = [" ", "GPortIn", "GPIO", "SPY",
|
||||
"VDD", "VSS", "DVDD", "DVSS",
|
||||
"PVDDTIE", "GPortOut"]
|
||||
PAD_SIZE = {"PVDD_08_08_NT_DR": 35,
|
||||
"PVSS_08_08_NT_DR": 35,
|
||||
"PDVDD_18_18_NT_DR": 35,
|
||||
"PDVSS_18_18_NT_DR": 35,
|
||||
"PDVDDTIE_18_18_NT_DR": 35,
|
||||
"PBIDIR_18_18_NT_DR": 30,
|
||||
"PINCNP_18_18_NT_DR": 25}
|
||||
|
||||
INITIAL_OFFSET = 55
|
||||
EDGE_OFFSET = 75
|
||||
TYPICAL_OFFSET = 50
|
||||
|
||||
|
||||
def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60)
|
||||
|
||||
|
||||
parser = argparse.ArgumentParser(formatter_class=formatter)
|
||||
|
||||
# Mandatory arguments
|
||||
parser.add_argument('--core_netlist', type=str, default="fpga_top_temp.v")
|
||||
parser.add_argument('--pinmap_file', type=str, default="./arch/pin_map.csv")
|
||||
parser.add_argument('--out_file', type=str, default="fpga22_Hie_top.v")
|
||||
args = parser.parse_args()
|
||||
|
||||
|
||||
def main():
|
||||
PinMapdf = LoadData(args.pinmap_file)
|
||||
TranslatePinNames(PinMapdf)
|
||||
print(PinMapdf.head(50))
|
||||
PortList = ParseInputVerilog()
|
||||
# Remove all the modules definition
|
||||
top = CreateTopWrapper(PortList, PinMapdf)
|
||||
modules = [each for each in top.submodule]
|
||||
for eachM in modules:
|
||||
del top.submodule[eachM]
|
||||
top.to_verilog(args.out_file)
|
||||
fix_verilog_format()
|
||||
CreateFloorPlanInfo(PinMapdf)
|
||||
IoRingPadConstraints(PinMapdf)
|
||||
GenerateDesignUPF(PinMapdf)
|
||||
|
||||
|
||||
def GenerateDesignUPF(PinMapdf):
|
||||
with open("power_intent.upf", "w") as fp:
|
||||
fp.write("## UPF Generate for the design\n\n")
|
||||
fp.write(
|
||||
"create_power_domain IO_RING_SUPPLY -elements {%s}\n" % " ".join(PinMapdf["Instance_Name"]))
|
||||
fp.write("\ncreate_power_domain SUPPLY_CORE -include_scope\n")
|
||||
fp.write("\n")
|
||||
fp.write("## ========== Create Connections ==========\n")
|
||||
fp.write("## ========== VDD 0.8V\n")
|
||||
fp.write("create_supply_port VDD -domain SUPPLY_CORE\n")
|
||||
fp.write("create_supply_net VDD -domain SUPPLY_CORE\n")
|
||||
fp.write("connect_supply_net VDD -ports VDD\n")
|
||||
fp.write("\n")
|
||||
fp.write("## ========== DVDD 1.8V\n")
|
||||
fp.write("create_supply_port DVDD -domain IO_RING_SUPPLY\n")
|
||||
fp.write("create_supply_net DVDD -domain IO_RING_SUPPLY\n")
|
||||
fp.write("connect_supply_net DVDD -ports DVDD\n")
|
||||
fp.write("\n")
|
||||
fp.write("## ========== VSS 0V\n")
|
||||
fp.write("create_supply_port VSS -domain SUPPLY_CORE\n")
|
||||
fp.write("create_supply_net VSS -domain SUPPLY_CORE\n")
|
||||
fp.write("connect_supply_net VSS -ports VSS\n")
|
||||
fp.write("\n")
|
||||
fp.write("## ========== VSS 0V\n")
|
||||
fp.write("create_supply_port DVSS -domain IO_RING_SUPPLY\n")
|
||||
fp.write("create_supply_net DVSS -domain IO_RING_SUPPLY\n")
|
||||
fp.write("connect_supply_net DVSS -ports DVSS\n")
|
||||
fp.write("\n")
|
||||
fp.write("set_domain_supply_net SUPPLY_CORE" +
|
||||
" -primary_power_net VDD -primary_ground_net VSS\n")
|
||||
fp.write("set_domain_supply_net IO_RING_SUPPLY" +
|
||||
" -primary_power_net DVDD -primary_ground_net DVSS\n")
|
||||
|
||||
|
||||
def CreateFloorPlanInfo(PinMapdf):
|
||||
NumberOfIOs = PinMapdf["Number"].max()
|
||||
DIE_HEIGHT = (100 + 65)*2 + \
|
||||
(6*EDGE_OFFSET) + \
|
||||
((NumberOfIOs-5)*TYPICAL_OFFSET)
|
||||
DIE_WIDTH = DIE_HEIGHT
|
||||
with open("proj_const.tcl", "w") as fp:
|
||||
fp.write("## Floorplan information generated by script\n")
|
||||
fp.write(f"set PADS_EACH_SIDE {NumberOfIOs}\n")
|
||||
fp.write(f"set DIE_HEIGHT {DIE_HEIGHT}\n")
|
||||
fp.write(f"set DIE_WIDTH {DIE_WIDTH}\n")
|
||||
|
||||
|
||||
def IoRingPadConstraints(PinMapdf):
|
||||
NumberOfIOs = PinMapdf["Number"].max()
|
||||
|
||||
PinMapdf['Pad_size'] = PinMapdf.apply(
|
||||
lambda row: PAD_SIZE[row.Cell], axis=1)
|
||||
PinMapdf['Pitch'] = PinMapdf.apply(
|
||||
lambda row: INITIAL_OFFSET if (row.Number == 1) else
|
||||
(EDGE_OFFSET if (row.Number <= 3) or (row.Number > (NumberOfIOs-2))
|
||||
else TYPICAL_OFFSET),
|
||||
axis=1)
|
||||
|
||||
for eachSide in range(1, 5):
|
||||
dfslice = PinMapdf[PinMapdf['Side'] == eachSide][[
|
||||
"Number", "Instance_Name", "Pitch", "Pad_size"]]
|
||||
dfslice.sort_values(by=['Number'])
|
||||
dfslice['Pad_pitch'] = dfslice['Pitch'].cumsum()
|
||||
dfslice['Distance'] = dfslice.apply(
|
||||
lambda row: row.Pad_pitch-((row.Pad_size)*0.5), axis=1)
|
||||
dfslice.to_csv(f"gpio_{SIDE_MAP[eachSide]}.csv", index=False)
|
||||
print(dfslice.head(10))
|
||||
with open("csv_pads.map", "w") as fp:
|
||||
fp.write("Instance_Name, Pad Name\n")
|
||||
fp.write("Distance, Offset Value\n")
|
||||
|
||||
|
||||
def fix_verilog_format():
|
||||
print("Running formatter")
|
||||
with open("tmp.v", "w") as fp:
|
||||
with open(args.out_file, "r") as fpr:
|
||||
for eachL in fpr.readlines():
|
||||
z = re.match("^.*\[(.*):(.*)].*$", eachL)
|
||||
if z:
|
||||
fIndex = z.groups()[0]
|
||||
eachL = eachL.replace(fIndex, str(eval(fIndex)))
|
||||
fp.write(eachL)
|
||||
os.remove(args.out_file)
|
||||
shutil.move("tmp.v", args.out_file)
|
||||
|
||||
|
||||
def CreateTopWrapper(PortList, PinMap):
|
||||
m = vgen.Module('fpga_top')
|
||||
uut = vgen.Module("fpga_core")
|
||||
uutportMap = []
|
||||
|
||||
# DVDD = m.Inout('DVDD_pad')
|
||||
# DVSS = m.Inout('DVSS_pad')
|
||||
for eachPin, prop in PortList.items():
|
||||
if ("gfpga" not in eachPin):
|
||||
prop["Port"] = eval(
|
||||
f"m.{prop['type']}('{eachPin}_pad',{prop['width']})")
|
||||
elif ("GPIO_Y" in eachPin):
|
||||
prop["Port"] = eval(
|
||||
f"m.{prop['type']}('gpio_pad',{prop['width']})")
|
||||
eval(f"uut.{prop['type']}('{eachPin}',{prop['width']})")
|
||||
prop["Wire"] = eval(f"m.Wire('{eachPin}',{prop['width']})")
|
||||
uutportMap.append((f'{eachPin}', prop["Wire"]))
|
||||
|
||||
# DVDD_W = m.Wire('DVDD')
|
||||
# DVSS_W = m.Wire('DVSS')
|
||||
SNS = m.Wire('SNS')
|
||||
RTO = m.Wire('RTO')
|
||||
LOW = m.Wire('TIELOW', 100)
|
||||
HIGH = m.Wire('TIEHIGH', 100)
|
||||
UNCONN = m.Wire('UNCONN', 100)
|
||||
# DVDD.assign(DVDD_W)
|
||||
# DVSS.assign(DVSS_W)
|
||||
unconnIndex = 0
|
||||
tieHighIndex = 0
|
||||
tieLowIndex = 0
|
||||
|
||||
m.Instance(uut, "fpga_core_uut", ports=tuple(uutportMap))
|
||||
PadInst = GPIO_PAD()
|
||||
|
||||
SLbl = ["None", "H", "H", "V", "V"]
|
||||
GPIOModulesInstance = {
|
||||
"PVDD_08_08_NT_DR": {"V": Power_Module("PVDD_08_08_NT_DR_V"),
|
||||
"H": Power_Module("PVDD_08_08_NT_DR_H")},
|
||||
"PVSS_08_08_NT_DR": {"V": Power_Module("PVSS_08_08_NT_DR_V"),
|
||||
"H": Power_Module("PVSS_08_08_NT_DR_H")},
|
||||
"PDVDD_18_18_NT_DR": {"V": Power_Module("PDVDD_18_18_NT_DR_V"),
|
||||
"H": Power_Module("PDVDD_18_18_NT_DR_H")},
|
||||
"PDVSS_18_18_NT_DR": {"V": Power_Module("PDVSS_18_18_NT_DR_V"),
|
||||
"H": Power_Module("PDVSS_18_18_NT_DR_H")},
|
||||
"PDVDDTIE_18_18_NT_DR": {"V": Power_Module("PDVDDTIE_18_18_NT_DR_V"),
|
||||
"H": Power_Module("PDVDDTIE_18_18_NT_DR_H")},
|
||||
"PBIDIR_18_18_NT_DR": {"V": PBIDIR_Module("PBIDIR_18_18_NT_DR_V"),
|
||||
"H": PBIDIR_Module("PBIDIR_18_18_NT_DR_H")},
|
||||
"PINCNP_18_18_NT_DR": {"V": PINCNP_Module("PINCNP_18_18_NT_DR_V"),
|
||||
"H": PINCNP_Module("PINCNP_18_18_NT_DR_H")}
|
||||
}
|
||||
PinMap["Instance_Name"] = ""
|
||||
for i in PinMap.index:
|
||||
# Common Pin Mapping and Instance Name
|
||||
portMap = (('SNS', SNS), ('RTO', RTO),)
|
||||
# ('DVDD', DVDD_W), ('DVSS', DVSS_W))
|
||||
inst = GPIOModulesInstance[PinMap["Cell"][i]][SLbl[PinMap["Side"][i]]]
|
||||
direc = SIDE_MAP[PinMap["Side"][i]]
|
||||
InstLabel = f"{PinMap['Cell'][i]}_{direc}_cell_{i}"
|
||||
PinMap["Instance_Name"][i] = InstLabel
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Power ports addition
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
if (PIN_MAP[PinMap["Pin"][i]] in ["VDD", "VSS", "DVDD", "DVSS", "PVDDTIE"]):
|
||||
pass
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Global Input Ports
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
elif (PIN_MAP[PinMap["Pin"][i]] == "GPortIn"):
|
||||
portMap += (("PAD", PortList[PinMap["Remark"][i]]["Port"]),)
|
||||
portMap += (("Y", PortList[PinMap["Remark"][i]]["Wire"]),)
|
||||
portMap += (("IE", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("IS", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("POE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PO", UNCONN[unconnIndex]),)
|
||||
unconnIndex += 1
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Global Output Ports
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
elif (PIN_MAP[PinMap["Pin"][i]] == "GPortOut"):
|
||||
portMap += (("PAD", PortList[PinMap["Remark"][i]]["Port"]),)
|
||||
portMap += (("A", PortList[PinMap["Remark"][i]]["Wire"]),)
|
||||
portMap += (("Y", UNCONN[unconnIndex]),)
|
||||
unconnIndex += 1
|
||||
portMap += (("IE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("OE", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("DS0", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("DS1", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("IS", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("POE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PS", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("SR", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PO", UNCONN[unconnIndex]),)
|
||||
unconnIndex += 1
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# GPIO Ports
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
elif (PIN_MAP[PinMap["Pin"][i]] == "GPIO"):
|
||||
BusName = PinMap["Remark"][i].split("[")[0]
|
||||
Index = int(PinMap["Remark"][i].split("[")[1][:1])
|
||||
portMap += (("PAD", PortList[BusName+"_Y"]["Port"][Index]),)
|
||||
for conn in ["Y", "A", "IE", "OE"]:
|
||||
portMap += ((conn, PortList[BusName +
|
||||
f"_{conn}"]["Wire"][Index]),)
|
||||
portMap += (("DS0", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("DS1", HIGH[tieHighIndex]),)
|
||||
tieHighIndex += 1
|
||||
portMap += (("IS", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("POE", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PS", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("SR", LOW[tieLowIndex]),)
|
||||
tieLowIndex += 1
|
||||
portMap += (("PO", UNCONN[unconnIndex]),)
|
||||
unconnIndex += 1
|
||||
else:
|
||||
print("Unknown Port needs...... terminating")
|
||||
exit()
|
||||
m.Instance(inst, InstLabel, ports=portMap)
|
||||
|
||||
# Adjust unconnected net width
|
||||
TIEH_INST = TIE_HIGH()
|
||||
TIEL_INST = TIE_LOW()
|
||||
for each in range(tieHighIndex):
|
||||
m.Instance(TIEH_INST, f"tie_high_{each}", ports=(("Y", HIGH[each]),))
|
||||
for each in range(tieLowIndex):
|
||||
m.Instance(TIEL_INST, f"tie_low_{each}", ports=(("Y", LOW[each]),))
|
||||
UNCONN.width = unconnIndex
|
||||
HIGH.width = tieHighIndex
|
||||
LOW.width = tieLowIndex
|
||||
return m
|
||||
|
||||
|
||||
def TranslatePinNames(df):
|
||||
df['Remark'] = df['Remark'].apply(
|
||||
lambda x: "gfpga_pad_GPIO[%d]" % int(x[4:]) if "GPIO" in x else x)
|
||||
df['Side'] = df['Side'].apply(lambda x: int(x))
|
||||
df['Pin'] = df['Pin'].apply(lambda x: int(x))
|
||||
df['Number'] = df['Number'].apply(lambda x: int(x))
|
||||
|
||||
|
||||
def LoadData(pathtoCsv=None):
|
||||
if pathtoCsv is None:
|
||||
pathtoCsv = r'https://docs.google.com/spreadsheets/d/e/2PACX-1vQoLR2KbvU9BOF6PszjTtIrrY7nrb8GlHMlqC_VAjFgGrTF5ToGgPvfDRY-Pj0GjgamkaIglq7kTX7q/pub?gid=85930648&single=true&output=csv'
|
||||
df = pd.read_csv(pathtoCsv, encoding='utf8', skiprows=1)
|
||||
df.dropna(subset=['Side', ], inplace=True)
|
||||
df = df.loc[:, ~df.columns.str.contains('^Unnamed')]
|
||||
dfNew = pd.DataFrame(columns=["Side", "Pin", "Number", "Remark", "Cell"])
|
||||
for i in range(4):
|
||||
dfTemp = pd.DataFrame(df.iloc[:, (5*i):5*(i+1)])
|
||||
dfTemp.columns = ["Side", "Pin", "Number", "Remark", "Cell"]
|
||||
dfNew = dfNew.append(dfTemp, ignore_index=True)
|
||||
return dfNew
|
||||
|
||||
|
||||
def ParseInputVerilog():
|
||||
astObj, _ = parse([args.core_netlist])
|
||||
ModuleDef = astObj.children()[0].children()[0].children()
|
||||
portlist = {}
|
||||
for eachPort in ModuleDef[1].ports:
|
||||
portlist[eachPort.name] = {"width": 0}
|
||||
|
||||
for eachPort in ModuleDef[2:]:
|
||||
if(isinstance(eachPort.children()[0], ast.Input)):
|
||||
portlist[eachPort.children()[0].name]["type"] = "Input"
|
||||
elif(isinstance(eachPort.children()[0], ast.Output)):
|
||||
portlist[eachPort.children()[0].name]["type"] = "Output"
|
||||
elif(isinstance(eachPort.children()[0], ast.Inout)):
|
||||
portlist[eachPort.children()[0].name]["type"] = "Inout"
|
||||
portlist[eachPort.children()[0].name]["width"] = 1 + \
|
||||
abs(int(eachPort.children()[0].width.msb.value) -
|
||||
int(eachPort.children()[0].width.lsb.value))
|
||||
print("* "*20)
|
||||
print("\n".join([(f"{port} : " +
|
||||
f"Width : {prop['width']} " +
|
||||
f"Dir : {prop['type']}") for port, prop in portlist.items()]))
|
||||
print("* "*20)
|
||||
return portlist
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
|
||||
def gpio_cell(name):
|
||||
m = vgen.Module(name)
|
||||
m.Inout('SNS')
|
||||
m.Inout('RTO')
|
||||
# m.Inout('DVDD')
|
||||
# m.Inout('DVSS')
|
||||
return m
|
||||
|
||||
|
||||
def Power_Module(cellName):
|
||||
m = gpio_cell(cellName)
|
||||
return m
|
||||
|
||||
|
||||
def PINCNP_Module(cellName):
|
||||
m = gpio_cell(cellName)
|
||||
m.Input("IE")
|
||||
m.Input("IS")
|
||||
m.Input("PAD")
|
||||
m.Input("POE")
|
||||
m.Input("PO")
|
||||
m.Output("Y")
|
||||
return m
|
||||
|
||||
|
||||
def PBIDIR_Module(cellName):
|
||||
m = PINCNP_Module(cellName)
|
||||
m.Input("A")
|
||||
m.Input("DS0")
|
||||
m.Input("DS1")
|
||||
m.Input("OE")
|
||||
m.Input("PE")
|
||||
m.Input("PS")
|
||||
m.Input("SR")
|
||||
return m
|
||||
|
||||
|
||||
def TIE_HIGH():
|
||||
m = vgen.Module('TIEHI_X1N_A9PP84TR_C14')
|
||||
m.Input("Y")
|
||||
return m
|
||||
|
||||
|
||||
def TIE_LOW():
|
||||
m = vgen.Module('TIELO_X1N_A9PP84TR_C14')
|
||||
m.Input("Y")
|
||||
return m
|
||||
|
||||
|
||||
def GPIO_PAD():
|
||||
m = vgen.Module('PBP50_18_18_NT_DR')
|
||||
m.Input("PAD")
|
||||
return m
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
remove_files = ["parsetab.py", "parser.out"]
|
||||
for eachFile in remove_files:
|
||||
if os.path.isfile(eachFile):
|
||||
os.remove(eachFile)
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
a 0.5 0.2
|
||||
b 0.5 0.2
|
||||
clk 0.5 0.2
|
||||
out_0 0.5 0.2
|
||||
out_1 0.5 0.2
|
||||
out_2 0.5 0.2
|
||||
out_3 0.5 0.2
|
||||
sum_0 0.5 0.2
|
||||
sum_1 0.5 0.2
|
||||
sum_2 0.5 0.2
|
||||
sum_3 0.5 0.2
|
||||
sum_4 0.5 0.2
|
||||
sum_5 0.5 0.2
|
||||
sum_6 0.5 0.2
|
||||
sum_7 0.5 0.2
|
||||
pipe_sum_0 0.5 0.2
|
||||
pipe_sum_1 0.5 0.2
|
||||
pipe_sum_2 0.5 0.2
|
||||
pipe_sum_3 0.5 0.2
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
.model test_mode_low
|
||||
.inputs a b clk
|
||||
.outputs out_0 out_1 out_2 out_3
|
||||
|
||||
.subckt shift D=a clk=clk Q=pipe_a_0
|
||||
.subckt shift D=pipe_a_0 clk=clk Q=pipe_a_1
|
||||
.subckt shift D=b clk=clk Q=pipe_b_0
|
||||
.subckt shift D=pipe_b_0 clk=clk Q=pipe_b_1
|
||||
|
||||
.latch sum_0 pipe_sum_0 re clk 0
|
||||
.latch sum_2 pipe_sum_1 re clk 0
|
||||
.latch sum_4 pipe_sum_2 re clk 0
|
||||
.latch sum_6 pipe_sum_3 re clk 0
|
||||
|
||||
.subckt adder a=pipe_a_0 b=pipe_b_0 cin=sum_7 cout=sum_1 sumout=sum_0
|
||||
.subckt adder a=pipe_sum_0 b=pipe_sum_2 cin=sum_1 cout=sum_3 sumout=sum_2
|
||||
.subckt adder a=pipe_sum_1 b=pipe_sum_3 cin=sum_3 cout=sum_5 sumout=sum_4
|
||||
.subckt adder a=pipe_sum_2 b=pipe_sum_0 cin=sum_5 cout=sum_7 sumout=sum_6
|
||||
|
||||
.names pipe_sum_0 out_0
|
||||
1 1
|
||||
.names pipe_sum_1 out_1
|
||||
1 1
|
||||
.names pipe_sum_2 out_2
|
||||
1 1
|
||||
.names pipe_sum_3 out_3
|
||||
1 1
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
//////////////////////////////////////
|
||||
// //
|
||||
// 2x2 Test-modes Low density //
|
||||
// //
|
||||
//////////////////////////////////////
|
||||
|
||||
|
||||
module test_mode_low (
|
||||
a,
|
||||
b,
|
||||
clk,
|
||||
reset,
|
||||
out );
|
||||
|
||||
input wire a;
|
||||
input wire b;
|
||||
input wire clk;
|
||||
input wire reset;
|
||||
output wire[3:0] out;
|
||||
|
||||
reg[1:0] pipe_a;
|
||||
reg[1:0] pipe_b;
|
||||
reg[3:0] pipe_sum;
|
||||
wire[7:0] sum;
|
||||
|
||||
assign sum[1:0] = pipe_a[1] + pipe_b[1] + sum[7];
|
||||
assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2];
|
||||
assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3];
|
||||
assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0];
|
||||
assign out = pipe_sum;
|
||||
|
||||
initial begin
|
||||
pipe_a <= 2'b00;
|
||||
pipe_b <= 2'b00;
|
||||
pipe_sum <= 4'b0000;
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(rst) begin
|
||||
pipe_a <= 2'b00;
|
||||
pipe_b <= 2'b00;
|
||||
pipe_b[1] <= pipe_b[0];
|
||||
pipe_sum <= 4'b0000;
|
||||
end else begin
|
||||
pipe_a[0] <= a;
|
||||
pipe_a[1] <= pipe_a[0];
|
||||
pipe_b[0] <= b;
|
||||
pipe_b[1] <= pipe_b[0];
|
||||
pipe_sum <= {sum[6], sum[4], sum[2], sum[0]};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 20
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing --duplicate_grid_pin #--verbose
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
||||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
module CCFFX1 ( // need to look deeper, we should have a reset signal!!
|
||||
input D,
|
||||
input CK,
|
||||
input R,
|
||||
output Q,
|
||||
output QB);
|
||||
|
||||
DFFRPQ_X1N_A9PP84TR_C14 DFFRPQ_X1N_A9PP84TR_C14_0 (.D(D), .Q(Q), .CK(CK), .R(R));
|
||||
INV_X1N_A9PP84TR_C14 INV_X1N_A9PP84TR_C14_0 (.A(Q), .Y(QB));
|
||||
endmodule
|
||||
|
||||
module GPIO (
|
||||
output A,
|
||||
output IE,
|
||||
output OE,
|
||||
input Y, // The output that is z
|
||||
input in,
|
||||
output out,
|
||||
input mem_out);
|
||||
|
||||
assign A = in;
|
||||
assign out = Y; // it is assign as if it was an input but it is not.
|
||||
assign IE = mem_out;
|
||||
INV_X1N_A9PP84TR_C14 ie_oe_inv (
|
||||
.A (mem_out),
|
||||
.Y (OE) );
|
||||
|
||||
endmodule
|
||||
|
||||
module dpram (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input[9:0] waddr,
|
||||
input[9:0] raddr,
|
||||
input[31:0] d_in,
|
||||
output[31:0] d_out );
|
||||
|
||||
wire LOW, HIGH;
|
||||
wire n_ren, n_wen;
|
||||
|
||||
TIELO_X1N_A9PP84TR_C14 Llevel (
|
||||
.Y (LOW) );
|
||||
|
||||
TIEHI_X1N_A9PP84TR_C14 Hlevel (
|
||||
.Y (HIGH) );
|
||||
|
||||
INV_X1N_A9PP84TR_C14 inv_ren (
|
||||
.A (ren),
|
||||
.Y (n_ren) );
|
||||
|
||||
INV_X1N_A9PP84TR_C14 inv_wen (
|
||||
.A (wen),
|
||||
.Y (n_wen) );
|
||||
|
||||
mem32x1024MW4_B4 memory_0 (
|
||||
.CLKA (clk), // Reading Port
|
||||
.CENA (n_ren),
|
||||
.AA (raddr),
|
||||
.QA (d_out),
|
||||
.DB (d_in), //Writing port
|
||||
.CLKB (clk),
|
||||
.CENB (n_wen),
|
||||
.AB (waddr),
|
||||
.STOV (LOW), //Self-Time Override -> for test -> should be set to zero
|
||||
.EMAA ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port A -> can slow down pulses if not set to zero
|
||||
.EMASA (LOW), // = 0 if STOV = 0
|
||||
.EMAB ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port B -> can slow down pulses if not set to zero => default value is 2
|
||||
.RET1N (HIGH) ); //Retention, active low
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
module CCFFX1 ( // need to look deeper, we should have a reset signal!!
|
||||
input D,
|
||||
input CK,
|
||||
input R,
|
||||
output Q,
|
||||
output QB);
|
||||
|
||||
DFFRPQ_X1N_A9PP84TR_C14 DFFRPQ_X1N_A9PP84TR_C14_0 (.D(D), .Q(Q), .CK(CK), .R(R));
|
||||
INV_X1N_A9PP84TR_C14 INV_X1N_A9PP84TR_C14_0 (.A(Q), .Y(QB));
|
||||
endmodule
|
||||
|
||||
module GPIO (
|
||||
output A,
|
||||
output IE,
|
||||
output OE,
|
||||
output Y,
|
||||
input in,
|
||||
output out,
|
||||
input mem_out);
|
||||
|
||||
assign A = in;
|
||||
assign out = Y;
|
||||
assign IE = mem_out;
|
||||
INV_X1N_A9PP84TR_C14 ie_oe_inv (
|
||||
.A (mem_out),
|
||||
.Y (OE) );
|
||||
|
||||
endmodule
|
||||
|
||||
module dpram (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input[9:0] waddr,
|
||||
input[9:0] raddr,
|
||||
input[31:0] d_in,
|
||||
output[31:0] d_out );
|
||||
|
||||
wire LOW, HIGH;
|
||||
wire n_ren, n_wen;
|
||||
|
||||
TIELO_X1N_A9PP84TR_C14 Llevel (
|
||||
.Y (LOW) );
|
||||
|
||||
TIEHI_X1N_A9PP84TR_C14 Hlevel (
|
||||
.Y (HIGH) );
|
||||
|
||||
INV_X1N_A9PP84TR_C14 inv_ren (
|
||||
.A (ren),
|
||||
.Y (n_ren) );
|
||||
|
||||
INV_X1N_A9PP84TR_C14 inv_wen (
|
||||
.A (wen),
|
||||
.Y (n_wen) );
|
||||
|
||||
mem32x1024MW4_B4 memory_0 (
|
||||
.CLKA (clk), // Reading Port
|
||||
.CENA (n_ren),
|
||||
.AA (raddr),
|
||||
.QA (d_out),
|
||||
.DB (d_in), //Writing port
|
||||
.CLKB (clk),
|
||||
.CENB (n_wen),
|
||||
.AB (waddr),
|
||||
.STOV (LOW), //Self-Time Override -> for test -> should be set to zero
|
||||
.EMAA ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port A -> can slow down pulses if not set to zero
|
||||
.EMASA (LOW), // = 0 if STOV = 0
|
||||
.EMAB ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port B -> can slow down pulses if not set to zero => default value is 2
|
||||
.RET1N (HIGH) ); //Retention, active low
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue