From 35fccf2214467e3021bdb7083aacfa1bf68d4cd9 Mon Sep 17 00:00:00 2001 From: CHARAS SAMY Date: Fri, 1 May 2020 15:56:05 -0600 Subject: [PATCH] Adding decoder task --- .../decoder_2_4/arch/fpga22_openfpga_arch.xml | 310 ++++ .../decoder_2_4/arch/fpga22_vpr_arch.xml | 682 +++++++++ .../tasks/decoder_2_4/arch/get_data.sh | 2 + .../k6_N10_SC_gf14_SCFF_2x2_homogeneous.xml | 1036 ++++++++++++++ .../tasks/decoder_2_4/arch/pin_map.csv | 20 + .../tasks/decoder_2_4/config/task.conf | 34 + .../tasks/decoder_2_4/fpga22_Hie_top.v | 1259 +++++++++++++++++ .../tasks/decoder_2_4/fpga_top_temp.v | 51 + .../tasks/decoder_2_4/generate_top.py | 408 ++++++ .../micro_benchmark/test_mode_low.act | 19 + .../micro_benchmark/test_mode_low.blif | 29 + .../micro_benchmark/test_mode_low.v | 53 + openfpga_flow/tasks/decoder_2_4/run.openfpga | 61 + .../decoder_2_4/sc_verilog/std_cell_extract.v | 73 + .../sc_verilog/std_cell_extract.v.bak | 73 + 15 files changed, 4110 insertions(+) create mode 100755 openfpga_flow/tasks/decoder_2_4/arch/fpga22_openfpga_arch.xml create mode 100755 openfpga_flow/tasks/decoder_2_4/arch/fpga22_vpr_arch.xml create mode 100755 openfpga_flow/tasks/decoder_2_4/arch/get_data.sh create mode 100755 openfpga_flow/tasks/decoder_2_4/arch/k6_N10_SC_gf14_SCFF_2x2_homogeneous.xml create mode 100755 openfpga_flow/tasks/decoder_2_4/arch/pin_map.csv create mode 100755 openfpga_flow/tasks/decoder_2_4/config/task.conf create mode 100755 openfpga_flow/tasks/decoder_2_4/fpga22_Hie_top.v create mode 100755 openfpga_flow/tasks/decoder_2_4/fpga_top_temp.v create mode 100755 openfpga_flow/tasks/decoder_2_4/generate_top.py create mode 100644 openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.act create mode 100644 openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.blif create mode 100644 openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.v create mode 100755 openfpga_flow/tasks/decoder_2_4/run.openfpga create mode 100755 openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v create mode 100755 openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v.bak diff --git a/openfpga_flow/tasks/decoder_2_4/arch/fpga22_openfpga_arch.xml b/openfpga_flow/tasks/decoder_2_4/arch/fpga22_openfpga_arch.xml new file mode 100755 index 000000000..a0728ad9c --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/arch/fpga22_openfpga_arch.xml @@ -0,0 +1,310 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/decoder_2_4/arch/fpga22_vpr_arch.xml b/openfpga_flow/tasks/decoder_2_4/arch/fpga22_vpr_arch.xml new file mode 100755 index 000000000..163a7e40f --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/arch/fpga22_vpr_arch.xml @@ -0,0 +1,682 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 180e-12 + 180e-12 + 180e-12 + 180e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/decoder_2_4/arch/get_data.sh b/openfpga_flow/tasks/decoder_2_4/arch/get_data.sh new file mode 100755 index 000000000..6efaf1e99 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/arch/get_data.sh @@ -0,0 +1,2 @@ +#!/bin/bash +wget –no-check-certificate -q -O - 'https://docs.google.com/spreadsheets/d/e/2PACX-1vQoLR2KbvU9BOF6PszjTtIrrY7nrb8GlHMlqC_VAjFgGrTF5ToGgPvfDRY-Pj0GjgamkaIglq7kTX7q/pub?gid=85930648&single=true&output=csv' > pin_map.csv \ No newline at end of file diff --git a/openfpga_flow/tasks/decoder_2_4/arch/k6_N10_SC_gf14_SCFF_2x2_homogeneous.xml b/openfpga_flow/tasks/decoder_2_4/arch/k6_N10_SC_gf14_SCFF_2x2_homogeneous.xml new file mode 100755 index 000000000..c9e5dc452 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/arch/k6_N10_SC_gf14_SCFF_2x2_homogeneous.xml @@ -0,0 +1,1036 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 180e-12 + 180e-12 + 180e-12 + 180e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/decoder_2_4/arch/pin_map.csv b/openfpga_flow/tasks/decoder_2_4/arch/pin_map.csv new file mode 100755 index 000000000..f7a9e2c86 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/arch/pin_map.csv @@ -0,0 +1,20 @@ +Left,,,,,,Right,,,,,,Top,,,,,,Bottom,,,,,,,,,, +Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,Side,Pin,Number,Remark,Cell,,,,,, +1,7,1,DVSS,PDVSS_18_18_NT_DR,,2,7,1,DVSS,PDVSS_18_18_NT_DR,,3,7,1,DVSS,PDVSS_18_18_NT_DR,,4,7,1,DVSS,PDVSS_18_18_NT_DR,,Code,Name,Instance,Count, +1,6,2,DVDD,PDVDD_18_18_NT_DR,,2,6,2,DVDD,PDVDD_18_18_NT_DR,,3,6,2,DVDD,PDVDD_18_18_NT_DR,,4,6,2,DVDD,PDVDD_18_18_NT_DR,,1,Global Port In,PINCNP_18_18_NT_DR,7,9 +1,1,3,Reset,PINCNP_18_18_NT_DR,,2,1,3,prog_clk,PINCNP_18_18_NT_DR,,3,1,3,sc_head,PINCNP_18_18_NT_DR,,4,1,3,ccff_head,PINCNP_18_18_NT_DR,,2,GPIO,PBIDIR_18_18_NT_DR,8,32 +1,2,4,GPIO1,PBIDIR_18_18_NT_DR,,2,2,4,GPIO4,PBIDIR_18_18_NT_DR,,3,2,4,GPIO7,PBIDIR_18_18_NT_DR,,4,2,4,GPIO2,PBIDIR_18_18_NT_DR,,3,SPY,PBIDIR_18_18_NT_DR,0,11 +1,1,5,clk,PINCNP_18_18_NT_DR,,2,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,3,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,4,8,5,PVDDTIE,PDVDDTIE_18_18_NT_DR,,4,VDD,PVDD_08_08_NT_DR,4, +1,2,6,GPIO0,PBIDIR_18_18_NT_DR,,2,2,6,GPIO5,PBIDIR_18_18_NT_DR,,3,2,6,GPIO6,PBIDIR_18_18_NT_DR,,4,2,6,GPIO3,PBIDIR_18_18_NT_DR,,5,VSS,PVSS_08_08_NT_DR,4, +1,1,7,Test_en,PINCNP_18_18_NT_DR,,2,1,7,pReset,PINCNP_18_18_NT_DR,,3,9,7,ccff_tail,PBIDIR_18_18_NT_DR,,4,9,7,sc_tail,PBIDIR_18_18_NT_DR,,6,DVDD,PDVDD_18_18_NT_DR,4, +1,4,8,VDD,PVDD_08_08_NT_DR,,2,4,8,VDD,PVDD_08_08_NT_DR,,3,4,8,VDD,PVDD_08_08_NT_DR,,4,4,8,VDD,PVDD_08_08_NT_DR,,7,DVSS,PDVSS_18_18_NT_DR,4, +1,5,9,VSS,PVSS_08_08_NT_DR,,2,5,9,VSS,PVSS_08_08_NT_DR,,3,5,9,VSS,PVSS_08_08_NT_DR,,4,5,9,VSS,PVSS_08_08_NT_DR,,8,PVDDTIE,PDVDDTIE_18_18_NT_DR,3, +,,,,,,,,,,,,,,,,,,,,,,,,9,Global Port Out,PBIDIR_18_18_NT_DR,2, +,,,,,,,,,,,,,,,,,,,,,,,,,,,36, +,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,"Things to Edit +1. Add respective numbers in the Pin column +2. Add pin name in pi name column (case inensetive will be converted to lower case all the time) +3. GPIO array is represented as GPIOxx +4. Orientation will be taken care by the script",,,, \ No newline at end of file diff --git a/openfpga_flow/tasks/decoder_2_4/config/task.conf b/openfpga_flow/tasks/decoder_2_4/config/task.conf new file mode 100755 index 000000000..432653d5f --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/run.openfpga +openfpga_shell_template = /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/release/FROG_v1.0/SCRIPTS/openfpga_script_templates/generate_testbench.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/arch/fpga22_openfpga_arch.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_task/arch/fpga22_vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.blif + +[SYNTHESIS_PARAM] +bench0_top = decoder_2_4 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/decoder_2_4/decoder_2_4.v +#bench0_chan_width = 200 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +# end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/decoder_2_4/fpga22_Hie_top.v b/openfpga_flow/tasks/decoder_2_4/fpga22_Hie_top.v new file mode 100755 index 000000000..b4db56263 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/fpga22_Hie_top.v @@ -0,0 +1,1259 @@ + + +module fpga_top +( + // inout DVDD_pad, + // inout DVSS_pad, + input [0:0] pReset_pad, + input [0:0] prog_clk_pad, + input [0:0] Reset_pad, + input [0:0] Test_en_pad, + input [0:0] clk_pad, + input [0:0] sc_head_pad, + output [0:0] sc_tail_pad, + inout [7:0] gpio_pad, + input [0:0] ccff_head_pad, + output [0:0] ccff_tail_pad +); + + wire [0:0] pReset; + wire [0:0] prog_clk; + wire [0:0] Reset; + wire [0:0] Test_en; + wire [0:0] clk; + wire [0:0] sc_head; + wire [0:0] sc_tail; + wire [7:0] gfpga_pad_GPIO_A; + wire [7:0] gfpga_pad_GPIO_IE; + wire [7:0] gfpga_pad_GPIO_OE; + wire [7:0] gfpga_pad_GPIO_Y; + wire [0:0] ccff_head; + wire [0:0] ccff_tail; + wire DVDD; + wire DVSS; + wire SNS; + wire RTO; + wire [65:0] TIELOW; + wire [28:0] TIEHIGH; + wire [18:0] UNCONN; + assign DVDD_pad = DVDD; + assign DVSS_pad = DVSS; + + fpga_core + fpga_core_uut + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Reset(Reset), + .Test_en(Test_en), + .clk(clk), + .sc_head(sc_head), + .sc_tail(sc_tail), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail) + ); + + + PDVSS_18_18_NT_DR_H + PDVSS_18_18_NT_DR_left_cell_0 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVDD_18_18_NT_DR_H + PDVDD_18_18_NT_DR_left_cell_1 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PINCNP_18_18_NT_DR_H + PINCNP_18_18_NT_DR_left_cell_2 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(Reset_pad), + .Y(Reset), + .IE(TIEHIGH[0]), + .IS(TIELOW[0]), + .POE(TIELOW[1]), + .PO(UNCONN[0]) + ); + + + PBIDIR_18_18_NT_DR_H + PBIDIR_18_18_NT_DR_left_cell_3 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[6]), + .Y(gfpga_pad_GPIO_Y[6]), + .A(gfpga_pad_GPIO_A[6]), + .IE(gfpga_pad_GPIO_IE[6]), + .OE(gfpga_pad_GPIO_OE[6]), + .DS0(TIEHIGH[1]), + .DS1(TIEHIGH[2]), + .IS(TIELOW[2]), + .PE(TIELOW[3]), + .POE(TIELOW[4]), + .PS(TIELOW[5]), + .SR(TIELOW[6]), + .PO(UNCONN[1]) + ); + + + PINCNP_18_18_NT_DR_H + PINCNP_18_18_NT_DR_left_cell_4 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(clk_pad), + .Y(clk), + .IE(TIEHIGH[3]), + .IS(TIELOW[7]), + .POE(TIELOW[8]), + .PO(UNCONN[2]) + ); + + + PBIDIR_18_18_NT_DR_H + PBIDIR_18_18_NT_DR_left_cell_5 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[7]), + .Y(gfpga_pad_GPIO_Y[7]), + .A(gfpga_pad_GPIO_A[7]), + .IE(gfpga_pad_GPIO_IE[7]), + .OE(gfpga_pad_GPIO_OE[7]), + .DS0(TIEHIGH[4]), + .DS1(TIEHIGH[5]), + .IS(TIELOW[9]), + .PE(TIELOW[10]), + .POE(TIELOW[11]), + .PS(TIELOW[12]), + .SR(TIELOW[13]), + .PO(UNCONN[3]) + ); + + + PINCNP_18_18_NT_DR_H + PINCNP_18_18_NT_DR_left_cell_6 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(Test_en_pad), + .Y(Test_en), + .IE(TIEHIGH[6]), + .IS(TIELOW[14]), + .POE(TIELOW[15]), + .PO(UNCONN[4]) + ); + + + PVDD_08_08_NT_DR_H + PVDD_08_08_NT_DR_left_cell_7 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PVSS_08_08_NT_DR_H + PVSS_08_08_NT_DR_left_cell_8 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVSS_18_18_NT_DR_H + PDVSS_18_18_NT_DR_right_cell_9 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVDD_18_18_NT_DR_H + PDVDD_18_18_NT_DR_right_cell_10 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PINCNP_18_18_NT_DR_H + PINCNP_18_18_NT_DR_right_cell_11 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(prog_clk_pad), + .Y(prog_clk), + .IE(TIEHIGH[7]), + .IS(TIELOW[16]), + .POE(TIELOW[17]), + .PO(UNCONN[5]) + ); + + + PBIDIR_18_18_NT_DR_H + PBIDIR_18_18_NT_DR_right_cell_12 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[0]), + .Y(gfpga_pad_GPIO_Y[0]), + .A(gfpga_pad_GPIO_A[0]), + .IE(gfpga_pad_GPIO_IE[0]), + .OE(gfpga_pad_GPIO_OE[0]), + .DS0(TIEHIGH[8]), + .DS1(TIEHIGH[9]), + .IS(TIELOW[18]), + .PE(TIELOW[19]), + .POE(TIELOW[20]), + .PS(TIELOW[21]), + .SR(TIELOW[22]), + .PO(UNCONN[6]) + ); + + + PDVDDTIE_18_18_NT_DR_H + PDVDDTIE_18_18_NT_DR_right_cell_13 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PBIDIR_18_18_NT_DR_H + PBIDIR_18_18_NT_DR_right_cell_14 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[1]), + .Y(gfpga_pad_GPIO_Y[1]), + .A(gfpga_pad_GPIO_A[1]), + .IE(gfpga_pad_GPIO_IE[1]), + .OE(gfpga_pad_GPIO_OE[1]), + .DS0(TIEHIGH[10]), + .DS1(TIEHIGH[11]), + .IS(TIELOW[23]), + .PE(TIELOW[24]), + .POE(TIELOW[25]), + .PS(TIELOW[26]), + .SR(TIELOW[27]), + .PO(UNCONN[7]) + ); + + + PINCNP_18_18_NT_DR_H + PINCNP_18_18_NT_DR_right_cell_15 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(pReset_pad), + .Y(pReset), + .IE(TIEHIGH[12]), + .IS(TIELOW[28]), + .POE(TIELOW[29]), + .PO(UNCONN[8]) + ); + + + PVDD_08_08_NT_DR_H + PVDD_08_08_NT_DR_right_cell_16 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PVSS_08_08_NT_DR_H + PVSS_08_08_NT_DR_right_cell_17 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVSS_18_18_NT_DR_V + PDVSS_18_18_NT_DR_top_cell_18 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVDD_18_18_NT_DR_V + PDVDD_18_18_NT_DR_top_cell_19 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PINCNP_18_18_NT_DR_V + PINCNP_18_18_NT_DR_top_cell_20 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(sc_head_pad), + .Y(sc_head), + .IE(TIEHIGH[13]), + .IS(TIELOW[30]), + .POE(TIELOW[31]), + .PO(UNCONN[9]) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_top_cell_21 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[2]), + .Y(gfpga_pad_GPIO_Y[2]), + .A(gfpga_pad_GPIO_A[2]), + .IE(gfpga_pad_GPIO_IE[2]), + .OE(gfpga_pad_GPIO_OE[2]), + .DS0(TIEHIGH[14]), + .DS1(TIEHIGH[15]), + .IS(TIELOW[32]), + .PE(TIELOW[33]), + .POE(TIELOW[34]), + .PS(TIELOW[35]), + .SR(TIELOW[36]), + .PO(UNCONN[10]) + ); + + + PDVDDTIE_18_18_NT_DR_V + PDVDDTIE_18_18_NT_DR_top_cell_22 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_top_cell_23 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[3]), + .Y(gfpga_pad_GPIO_Y[3]), + .A(gfpga_pad_GPIO_A[3]), + .IE(gfpga_pad_GPIO_IE[3]), + .OE(gfpga_pad_GPIO_OE[3]), + .DS0(TIEHIGH[16]), + .DS1(TIEHIGH[17]), + .IS(TIELOW[37]), + .PE(TIELOW[38]), + .POE(TIELOW[39]), + .PS(TIELOW[40]), + .SR(TIELOW[41]), + .PO(UNCONN[11]) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_top_cell_24 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(ccff_tail_pad), + .A(ccff_tail), + .Y(UNCONN[12]), + .IE(TIELOW[42]), + .OE(TIEHIGH[18]), + .DS0(TIEHIGH[19]), + .DS1(TIEHIGH[20]), + .IS(TIELOW[43]), + .PE(TIELOW[44]), + .POE(TIELOW[45]), + .PS(TIELOW[46]), + .SR(TIELOW[47]), + .PO(UNCONN[13]) + ); + + + PVDD_08_08_NT_DR_V + PVDD_08_08_NT_DR_top_cell_25 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PVSS_08_08_NT_DR_V + PVSS_08_08_NT_DR_top_cell_26 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVSS_18_18_NT_DR_V + PDVSS_18_18_NT_DR_bottom_cell_27 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PDVDD_18_18_NT_DR_V + PDVDD_18_18_NT_DR_bottom_cell_28 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PINCNP_18_18_NT_DR_V + PINCNP_18_18_NT_DR_bottom_cell_29 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(ccff_head_pad), + .Y(ccff_head), + .IE(TIEHIGH[21]), + .IS(TIELOW[48]), + .POE(TIELOW[49]), + .PO(UNCONN[14]) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_bottom_cell_30 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[4]), + .Y(gfpga_pad_GPIO_Y[4]), + .A(gfpga_pad_GPIO_A[4]), + .IE(gfpga_pad_GPIO_IE[4]), + .OE(gfpga_pad_GPIO_OE[4]), + .DS0(TIEHIGH[22]), + .DS1(TIEHIGH[23]), + .IS(TIELOW[50]), + .PE(TIELOW[51]), + .POE(TIELOW[52]), + .PS(TIELOW[53]), + .SR(TIELOW[54]), + .PO(UNCONN[15]) + ); + + + PDVDDTIE_18_18_NT_DR_V + PDVDDTIE_18_18_NT_DR_bottom_cell_31 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_bottom_cell_32 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(gpio_pad[5]), + .Y(gfpga_pad_GPIO_Y[5]), + .A(gfpga_pad_GPIO_A[5]), + .IE(gfpga_pad_GPIO_IE[5]), + .OE(gfpga_pad_GPIO_OE[5]), + .DS0(TIEHIGH[24]), + .DS1(TIEHIGH[25]), + .IS(TIELOW[55]), + .PE(TIELOW[56]), + .POE(TIELOW[57]), + .PS(TIELOW[58]), + .SR(TIELOW[59]), + .PO(UNCONN[16]) + ); + + + PBIDIR_18_18_NT_DR_V + PBIDIR_18_18_NT_DR_bottom_cell_33 + ( + .SNS(SNS), + .RTO(RTO), + // .DVDD(DVDD), + // .DVSS(DVSS), + .PAD(sc_tail_pad), + .A(sc_tail), + .Y(UNCONN[17]), + .IE(TIELOW[60]), + .OE(TIEHIGH[26]), + .DS0(TIEHIGH[27]), + .DS1(TIEHIGH[28]), + .IS(TIELOW[61]), + .PE(TIELOW[62]), + .POE(TIELOW[63]), + .PS(TIELOW[64]), + .SR(TIELOW[65]), + .PO(UNCONN[18]) + ); + + + PVDD_08_08_NT_DR_V + PVDD_08_08_NT_DR_bottom_cell_34 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + PVSS_08_08_NT_DR_V + PVSS_08_08_NT_DR_bottom_cell_35 + ( + .SNS(SNS), + .RTO(RTO) + // .DVDD(DVDD), + // .DVSS(DVSS) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_0 + ( + .Y(TIEHIGH[0]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_1 + ( + .Y(TIEHIGH[1]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_2 + ( + .Y(TIEHIGH[2]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_3 + ( + .Y(TIEHIGH[3]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_4 + ( + .Y(TIEHIGH[4]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_5 + ( + .Y(TIEHIGH[5]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_6 + ( + .Y(TIEHIGH[6]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_7 + ( + .Y(TIEHIGH[7]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_8 + ( + .Y(TIEHIGH[8]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_9 + ( + .Y(TIEHIGH[9]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_10 + ( + .Y(TIEHIGH[10]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_11 + ( + .Y(TIEHIGH[11]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_12 + ( + .Y(TIEHIGH[12]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_13 + ( + .Y(TIEHIGH[13]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_14 + ( + .Y(TIEHIGH[14]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_15 + ( + .Y(TIEHIGH[15]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_16 + ( + .Y(TIEHIGH[16]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_17 + ( + .Y(TIEHIGH[17]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_18 + ( + .Y(TIEHIGH[18]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_19 + ( + .Y(TIEHIGH[19]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_20 + ( + .Y(TIEHIGH[20]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_21 + ( + .Y(TIEHIGH[21]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_22 + ( + .Y(TIEHIGH[22]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_23 + ( + .Y(TIEHIGH[23]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_24 + ( + .Y(TIEHIGH[24]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_25 + ( + .Y(TIEHIGH[25]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_26 + ( + .Y(TIEHIGH[26]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_27 + ( + .Y(TIEHIGH[27]) + ); + + + TIEHI_X1N_A9PP84TR_C14 + tie_high_28 + ( + .Y(TIEHIGH[28]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_0 + ( + .Y(TIELOW[0]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_1 + ( + .Y(TIELOW[1]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_2 + ( + .Y(TIELOW[2]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_3 + ( + .Y(TIELOW[3]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_4 + ( + .Y(TIELOW[4]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_5 + ( + .Y(TIELOW[5]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_6 + ( + .Y(TIELOW[6]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_7 + ( + .Y(TIELOW[7]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_8 + ( + .Y(TIELOW[8]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_9 + ( + .Y(TIELOW[9]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_10 + ( + .Y(TIELOW[10]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_11 + ( + .Y(TIELOW[11]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_12 + ( + .Y(TIELOW[12]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_13 + ( + .Y(TIELOW[13]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_14 + ( + .Y(TIELOW[14]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_15 + ( + .Y(TIELOW[15]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_16 + ( + .Y(TIELOW[16]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_17 + ( + .Y(TIELOW[17]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_18 + ( + .Y(TIELOW[18]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_19 + ( + .Y(TIELOW[19]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_20 + ( + .Y(TIELOW[20]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_21 + ( + .Y(TIELOW[21]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_22 + ( + .Y(TIELOW[22]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_23 + ( + .Y(TIELOW[23]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_24 + ( + .Y(TIELOW[24]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_25 + ( + .Y(TIELOW[25]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_26 + ( + .Y(TIELOW[26]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_27 + ( + .Y(TIELOW[27]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_28 + ( + .Y(TIELOW[28]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_29 + ( + .Y(TIELOW[29]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_30 + ( + .Y(TIELOW[30]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_31 + ( + .Y(TIELOW[31]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_32 + ( + .Y(TIELOW[32]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_33 + ( + .Y(TIELOW[33]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_34 + ( + .Y(TIELOW[34]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_35 + ( + .Y(TIELOW[35]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_36 + ( + .Y(TIELOW[36]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_37 + ( + .Y(TIELOW[37]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_38 + ( + .Y(TIELOW[38]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_39 + ( + .Y(TIELOW[39]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_40 + ( + .Y(TIELOW[40]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_41 + ( + .Y(TIELOW[41]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_42 + ( + .Y(TIELOW[42]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_43 + ( + .Y(TIELOW[43]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_44 + ( + .Y(TIELOW[44]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_45 + ( + .Y(TIELOW[45]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_46 + ( + .Y(TIELOW[46]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_47 + ( + .Y(TIELOW[47]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_48 + ( + .Y(TIELOW[48]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_49 + ( + .Y(TIELOW[49]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_50 + ( + .Y(TIELOW[50]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_51 + ( + .Y(TIELOW[51]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_52 + ( + .Y(TIELOW[52]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_53 + ( + .Y(TIELOW[53]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_54 + ( + .Y(TIELOW[54]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_55 + ( + .Y(TIELOW[55]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_56 + ( + .Y(TIELOW[56]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_57 + ( + .Y(TIELOW[57]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_58 + ( + .Y(TIELOW[58]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_59 + ( + .Y(TIELOW[59]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_60 + ( + .Y(TIELOW[60]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_61 + ( + .Y(TIELOW[61]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_62 + ( + .Y(TIELOW[62]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_63 + ( + .Y(TIELOW[63]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_64 + ( + .Y(TIELOW[64]) + ); + + + TIELO_X1N_A9PP84TR_C14 + tie_low_65 + ( + .Y(TIELOW[65]) + ); + + +endmodule + diff --git a/openfpga_flow/tasks/decoder_2_4/fpga_top_temp.v b/openfpga_flow/tasks/decoder_2_4/fpga_top_temp.v new file mode 100755 index 000000000..da57a8112 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/fpga_top_temp.v @@ -0,0 +1,51 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Top-level Verilog module for FPGA +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Apr 22 16:46:21 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ----- Verilog module for fpga_top ----- +module fpga_core(pReset, + prog_clk, + Reset, + Test_en, + clk, + sc_head, + sc_tail, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + ccff_head, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] Reset; +//----- GLOBAL PORTS ----- +input [0:0] Test_en; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- GPOUT PORTS ----- +output [0:7] gfpga_pad_GPIO_A; +//----- GPOUT PORTS ----- +output [0:7] gfpga_pad_GPIO_IE; +//----- GPOUT PORTS ----- +output [0:7] gfpga_pad_GPIO_OE; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_Y; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +input [0:0]sc_head; +output [0:0]sc_tail; +//----- BEGIN wire-connection ports ----- +endmodule diff --git a/openfpga_flow/tasks/decoder_2_4/generate_top.py b/openfpga_flow/tasks/decoder_2_4/generate_top.py new file mode 100755 index 000000000..6b08ee1c0 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/generate_top.py @@ -0,0 +1,408 @@ +# THis script creates top level wrapper for the FPGA Core +# THe GPIo Pin assignement can be provided with csv file or +# Link to google published sheet +import veriloggen as vgen +import pyverilog.utils.version +import sys +from pyverilog.vparser import ast +from pyverilog.vparser.parser import parse +import pandas as pd +import os +import re +import shutil +import argparse + + +SIDE_MAP = ["", "left", "right", "top", "bottom"] + +PIN_MAP = [" ", "GPortIn", "GPIO", "SPY", + "VDD", "VSS", "DVDD", "DVSS", + "PVDDTIE", "GPortOut"] +PAD_SIZE = {"PVDD_08_08_NT_DR": 35, + "PVSS_08_08_NT_DR": 35, + "PDVDD_18_18_NT_DR": 35, + "PDVSS_18_18_NT_DR": 35, + "PDVDDTIE_18_18_NT_DR": 35, + "PBIDIR_18_18_NT_DR": 30, + "PINCNP_18_18_NT_DR": 25} + +INITIAL_OFFSET = 55 +EDGE_OFFSET = 75 +TYPICAL_OFFSET = 50 + + +def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60) + + +parser = argparse.ArgumentParser(formatter_class=formatter) + +# Mandatory arguments +parser.add_argument('--core_netlist', type=str, default="fpga_top_temp.v") +parser.add_argument('--pinmap_file', type=str, default="./arch/pin_map.csv") +parser.add_argument('--out_file', type=str, default="fpga22_Hie_top.v") +args = parser.parse_args() + + +def main(): + PinMapdf = LoadData(args.pinmap_file) + TranslatePinNames(PinMapdf) + print(PinMapdf.head(50)) + PortList = ParseInputVerilog() + # Remove all the modules definition + top = CreateTopWrapper(PortList, PinMapdf) + modules = [each for each in top.submodule] + for eachM in modules: + del top.submodule[eachM] + top.to_verilog(args.out_file) + fix_verilog_format() + CreateFloorPlanInfo(PinMapdf) + IoRingPadConstraints(PinMapdf) + GenerateDesignUPF(PinMapdf) + + +def GenerateDesignUPF(PinMapdf): + with open("power_intent.upf", "w") as fp: + fp.write("## UPF Generate for the design\n\n") + fp.write( + "create_power_domain IO_RING_SUPPLY -elements {%s}\n" % " ".join(PinMapdf["Instance_Name"])) + fp.write("\ncreate_power_domain SUPPLY_CORE -include_scope\n") + fp.write("\n") + fp.write("## ========== Create Connections ==========\n") + fp.write("## ========== VDD 0.8V\n") + fp.write("create_supply_port VDD -domain SUPPLY_CORE\n") + fp.write("create_supply_net VDD -domain SUPPLY_CORE\n") + fp.write("connect_supply_net VDD -ports VDD\n") + fp.write("\n") + fp.write("## ========== DVDD 1.8V\n") + fp.write("create_supply_port DVDD -domain IO_RING_SUPPLY\n") + fp.write("create_supply_net DVDD -domain IO_RING_SUPPLY\n") + fp.write("connect_supply_net DVDD -ports DVDD\n") + fp.write("\n") + fp.write("## ========== VSS 0V\n") + fp.write("create_supply_port VSS -domain SUPPLY_CORE\n") + fp.write("create_supply_net VSS -domain SUPPLY_CORE\n") + fp.write("connect_supply_net VSS -ports VSS\n") + fp.write("\n") + fp.write("## ========== VSS 0V\n") + fp.write("create_supply_port DVSS -domain IO_RING_SUPPLY\n") + fp.write("create_supply_net DVSS -domain IO_RING_SUPPLY\n") + fp.write("connect_supply_net DVSS -ports DVSS\n") + fp.write("\n") + fp.write("set_domain_supply_net SUPPLY_CORE" + + " -primary_power_net VDD -primary_ground_net VSS\n") + fp.write("set_domain_supply_net IO_RING_SUPPLY" + + " -primary_power_net DVDD -primary_ground_net DVSS\n") + + +def CreateFloorPlanInfo(PinMapdf): + NumberOfIOs = PinMapdf["Number"].max() + DIE_HEIGHT = (100 + 65)*2 + \ + (6*EDGE_OFFSET) + \ + ((NumberOfIOs-5)*TYPICAL_OFFSET) + DIE_WIDTH = DIE_HEIGHT + with open("proj_const.tcl", "w") as fp: + fp.write("## Floorplan information generated by script\n") + fp.write(f"set PADS_EACH_SIDE {NumberOfIOs}\n") + fp.write(f"set DIE_HEIGHT {DIE_HEIGHT}\n") + fp.write(f"set DIE_WIDTH {DIE_WIDTH}\n") + + +def IoRingPadConstraints(PinMapdf): + NumberOfIOs = PinMapdf["Number"].max() + + PinMapdf['Pad_size'] = PinMapdf.apply( + lambda row: PAD_SIZE[row.Cell], axis=1) + PinMapdf['Pitch'] = PinMapdf.apply( + lambda row: INITIAL_OFFSET if (row.Number == 1) else + (EDGE_OFFSET if (row.Number <= 3) or (row.Number > (NumberOfIOs-2)) + else TYPICAL_OFFSET), + axis=1) + + for eachSide in range(1, 5): + dfslice = PinMapdf[PinMapdf['Side'] == eachSide][[ + "Number", "Instance_Name", "Pitch", "Pad_size"]] + dfslice.sort_values(by=['Number']) + dfslice['Pad_pitch'] = dfslice['Pitch'].cumsum() + dfslice['Distance'] = dfslice.apply( + lambda row: row.Pad_pitch-((row.Pad_size)*0.5), axis=1) + dfslice.to_csv(f"gpio_{SIDE_MAP[eachSide]}.csv", index=False) + print(dfslice.head(10)) + with open("csv_pads.map", "w") as fp: + fp.write("Instance_Name, Pad Name\n") + fp.write("Distance, Offset Value\n") + + +def fix_verilog_format(): + print("Running formatter") + with open("tmp.v", "w") as fp: + with open(args.out_file, "r") as fpr: + for eachL in fpr.readlines(): + z = re.match("^.*\[(.*):(.*)].*$", eachL) + if z: + fIndex = z.groups()[0] + eachL = eachL.replace(fIndex, str(eval(fIndex))) + fp.write(eachL) + os.remove(args.out_file) + shutil.move("tmp.v", args.out_file) + + +def CreateTopWrapper(PortList, PinMap): + m = vgen.Module('fpga_top') + uut = vgen.Module("fpga_core") + uutportMap = [] + + # DVDD = m.Inout('DVDD_pad') + # DVSS = m.Inout('DVSS_pad') + for eachPin, prop in PortList.items(): + if ("gfpga" not in eachPin): + prop["Port"] = eval( + f"m.{prop['type']}('{eachPin}_pad',{prop['width']})") + elif ("GPIO_Y" in eachPin): + prop["Port"] = eval( + f"m.{prop['type']}('gpio_pad',{prop['width']})") + eval(f"uut.{prop['type']}('{eachPin}',{prop['width']})") + prop["Wire"] = eval(f"m.Wire('{eachPin}',{prop['width']})") + uutportMap.append((f'{eachPin}', prop["Wire"])) + + # DVDD_W = m.Wire('DVDD') + # DVSS_W = m.Wire('DVSS') + SNS = m.Wire('SNS') + RTO = m.Wire('RTO') + LOW = m.Wire('TIELOW', 100) + HIGH = m.Wire('TIEHIGH', 100) + UNCONN = m.Wire('UNCONN', 100) + # DVDD.assign(DVDD_W) + # DVSS.assign(DVSS_W) + unconnIndex = 0 + tieHighIndex = 0 + tieLowIndex = 0 + + m.Instance(uut, "fpga_core_uut", ports=tuple(uutportMap)) + PadInst = GPIO_PAD() + + SLbl = ["None", "H", "H", "V", "V"] + GPIOModulesInstance = { + "PVDD_08_08_NT_DR": {"V": Power_Module("PVDD_08_08_NT_DR_V"), + "H": Power_Module("PVDD_08_08_NT_DR_H")}, + "PVSS_08_08_NT_DR": {"V": Power_Module("PVSS_08_08_NT_DR_V"), + "H": Power_Module("PVSS_08_08_NT_DR_H")}, + "PDVDD_18_18_NT_DR": {"V": Power_Module("PDVDD_18_18_NT_DR_V"), + "H": Power_Module("PDVDD_18_18_NT_DR_H")}, + "PDVSS_18_18_NT_DR": {"V": Power_Module("PDVSS_18_18_NT_DR_V"), + "H": Power_Module("PDVSS_18_18_NT_DR_H")}, + "PDVDDTIE_18_18_NT_DR": {"V": Power_Module("PDVDDTIE_18_18_NT_DR_V"), + "H": Power_Module("PDVDDTIE_18_18_NT_DR_H")}, + "PBIDIR_18_18_NT_DR": {"V": PBIDIR_Module("PBIDIR_18_18_NT_DR_V"), + "H": PBIDIR_Module("PBIDIR_18_18_NT_DR_H")}, + "PINCNP_18_18_NT_DR": {"V": PINCNP_Module("PINCNP_18_18_NT_DR_V"), + "H": PINCNP_Module("PINCNP_18_18_NT_DR_H")} + } + PinMap["Instance_Name"] = "" + for i in PinMap.index: + # Common Pin Mapping and Instance Name + portMap = (('SNS', SNS), ('RTO', RTO),) + # ('DVDD', DVDD_W), ('DVSS', DVSS_W)) + inst = GPIOModulesInstance[PinMap["Cell"][i]][SLbl[PinMap["Side"][i]]] + direc = SIDE_MAP[PinMap["Side"][i]] + InstLabel = f"{PinMap['Cell'][i]}_{direc}_cell_{i}" + PinMap["Instance_Name"][i] = InstLabel + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Power ports addition + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + if (PIN_MAP[PinMap["Pin"][i]] in ["VDD", "VSS", "DVDD", "DVSS", "PVDDTIE"]): + pass + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Global Input Ports + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + elif (PIN_MAP[PinMap["Pin"][i]] == "GPortIn"): + portMap += (("PAD", PortList[PinMap["Remark"][i]]["Port"]),) + portMap += (("Y", PortList[PinMap["Remark"][i]]["Wire"]),) + portMap += (("IE", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("IS", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("POE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PO", UNCONN[unconnIndex]),) + unconnIndex += 1 + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Global Output Ports + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + elif (PIN_MAP[PinMap["Pin"][i]] == "GPortOut"): + portMap += (("PAD", PortList[PinMap["Remark"][i]]["Port"]),) + portMap += (("A", PortList[PinMap["Remark"][i]]["Wire"]),) + portMap += (("Y", UNCONN[unconnIndex]),) + unconnIndex += 1 + portMap += (("IE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("OE", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("DS0", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("DS1", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("IS", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("POE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PS", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("SR", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PO", UNCONN[unconnIndex]),) + unconnIndex += 1 + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # GPIO Ports + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + elif (PIN_MAP[PinMap["Pin"][i]] == "GPIO"): + BusName = PinMap["Remark"][i].split("[")[0] + Index = int(PinMap["Remark"][i].split("[")[1][:1]) + portMap += (("PAD", PortList[BusName+"_Y"]["Port"][Index]),) + for conn in ["Y", "A", "IE", "OE"]: + portMap += ((conn, PortList[BusName + + f"_{conn}"]["Wire"][Index]),) + portMap += (("DS0", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("DS1", HIGH[tieHighIndex]),) + tieHighIndex += 1 + portMap += (("IS", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("POE", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PS", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("SR", LOW[tieLowIndex]),) + tieLowIndex += 1 + portMap += (("PO", UNCONN[unconnIndex]),) + unconnIndex += 1 + else: + print("Unknown Port needs...... terminating") + exit() + m.Instance(inst, InstLabel, ports=portMap) + + # Adjust unconnected net width + TIEH_INST = TIE_HIGH() + TIEL_INST = TIE_LOW() + for each in range(tieHighIndex): + m.Instance(TIEH_INST, f"tie_high_{each}", ports=(("Y", HIGH[each]),)) + for each in range(tieLowIndex): + m.Instance(TIEL_INST, f"tie_low_{each}", ports=(("Y", LOW[each]),)) + UNCONN.width = unconnIndex + HIGH.width = tieHighIndex + LOW.width = tieLowIndex + return m + + +def TranslatePinNames(df): + df['Remark'] = df['Remark'].apply( + lambda x: "gfpga_pad_GPIO[%d]" % int(x[4:]) if "GPIO" in x else x) + df['Side'] = df['Side'].apply(lambda x: int(x)) + df['Pin'] = df['Pin'].apply(lambda x: int(x)) + df['Number'] = df['Number'].apply(lambda x: int(x)) + + +def LoadData(pathtoCsv=None): + if pathtoCsv is None: + pathtoCsv = r'https://docs.google.com/spreadsheets/d/e/2PACX-1vQoLR2KbvU9BOF6PszjTtIrrY7nrb8GlHMlqC_VAjFgGrTF5ToGgPvfDRY-Pj0GjgamkaIglq7kTX7q/pub?gid=85930648&single=true&output=csv' + df = pd.read_csv(pathtoCsv, encoding='utf8', skiprows=1) + df.dropna(subset=['Side', ], inplace=True) + df = df.loc[:, ~df.columns.str.contains('^Unnamed')] + dfNew = pd.DataFrame(columns=["Side", "Pin", "Number", "Remark", "Cell"]) + for i in range(4): + dfTemp = pd.DataFrame(df.iloc[:, (5*i):5*(i+1)]) + dfTemp.columns = ["Side", "Pin", "Number", "Remark", "Cell"] + dfNew = dfNew.append(dfTemp, ignore_index=True) + return dfNew + + +def ParseInputVerilog(): + astObj, _ = parse([args.core_netlist]) + ModuleDef = astObj.children()[0].children()[0].children() + portlist = {} + for eachPort in ModuleDef[1].ports: + portlist[eachPort.name] = {"width": 0} + + for eachPort in ModuleDef[2:]: + if(isinstance(eachPort.children()[0], ast.Input)): + portlist[eachPort.children()[0].name]["type"] = "Input" + elif(isinstance(eachPort.children()[0], ast.Output)): + portlist[eachPort.children()[0].name]["type"] = "Output" + elif(isinstance(eachPort.children()[0], ast.Inout)): + portlist[eachPort.children()[0].name]["type"] = "Inout" + portlist[eachPort.children()[0].name]["width"] = 1 + \ + abs(int(eachPort.children()[0].width.msb.value) - + int(eachPort.children()[0].width.lsb.value)) + print("* "*20) + print("\n".join([(f"{port} : " + + f"Width : {prop['width']} " + + f"Dir : {prop['type']}") for port, prop in portlist.items()])) + print("* "*20) + return portlist +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + +def gpio_cell(name): + m = vgen.Module(name) + m.Inout('SNS') + m.Inout('RTO') + # m.Inout('DVDD') + # m.Inout('DVSS') + return m + + +def Power_Module(cellName): + m = gpio_cell(cellName) + return m + + +def PINCNP_Module(cellName): + m = gpio_cell(cellName) + m.Input("IE") + m.Input("IS") + m.Input("PAD") + m.Input("POE") + m.Input("PO") + m.Output("Y") + return m + + +def PBIDIR_Module(cellName): + m = PINCNP_Module(cellName) + m.Input("A") + m.Input("DS0") + m.Input("DS1") + m.Input("OE") + m.Input("PE") + m.Input("PS") + m.Input("SR") + return m + + +def TIE_HIGH(): + m = vgen.Module('TIEHI_X1N_A9PP84TR_C14') + m.Input("Y") + return m + + +def TIE_LOW(): + m = vgen.Module('TIELO_X1N_A9PP84TR_C14') + m.Input("Y") + return m + + +def GPIO_PAD(): + m = vgen.Module('PBP50_18_18_NT_DR') + m.Input("PAD") + return m + + +if __name__ == '__main__': + main() + remove_files = ["parsetab.py", "parser.out"] + for eachFile in remove_files: + if os.path.isfile(eachFile): + os.remove(eachFile) diff --git a/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.act b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.act new file mode 100644 index 000000000..7d80f8677 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.act @@ -0,0 +1,19 @@ +a 0.5 0.2 +b 0.5 0.2 +clk 0.5 0.2 +out_0 0.5 0.2 +out_1 0.5 0.2 +out_2 0.5 0.2 +out_3 0.5 0.2 +sum_0 0.5 0.2 +sum_1 0.5 0.2 +sum_2 0.5 0.2 +sum_3 0.5 0.2 +sum_4 0.5 0.2 +sum_5 0.5 0.2 +sum_6 0.5 0.2 +sum_7 0.5 0.2 +pipe_sum_0 0.5 0.2 +pipe_sum_1 0.5 0.2 +pipe_sum_2 0.5 0.2 +pipe_sum_3 0.5 0.2 diff --git a/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.blif b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.blif new file mode 100644 index 000000000..2275d87c8 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.blif @@ -0,0 +1,29 @@ +.model test_mode_low +.inputs a b clk +.outputs out_0 out_1 out_2 out_3 + +.subckt shift D=a clk=clk Q=pipe_a_0 +.subckt shift D=pipe_a_0 clk=clk Q=pipe_a_1 +.subckt shift D=b clk=clk Q=pipe_b_0 +.subckt shift D=pipe_b_0 clk=clk Q=pipe_b_1 + +.latch sum_0 pipe_sum_0 re clk 0 +.latch sum_2 pipe_sum_1 re clk 0 +.latch sum_4 pipe_sum_2 re clk 0 +.latch sum_6 pipe_sum_3 re clk 0 + +.subckt adder a=pipe_a_0 b=pipe_b_0 cin=sum_7 cout=sum_1 sumout=sum_0 +.subckt adder a=pipe_sum_0 b=pipe_sum_2 cin=sum_1 cout=sum_3 sumout=sum_2 +.subckt adder a=pipe_sum_1 b=pipe_sum_3 cin=sum_3 cout=sum_5 sumout=sum_4 +.subckt adder a=pipe_sum_2 b=pipe_sum_0 cin=sum_5 cout=sum_7 sumout=sum_6 + +.names pipe_sum_0 out_0 +1 1 +.names pipe_sum_1 out_1 +1 1 +.names pipe_sum_2 out_2 +1 1 +.names pipe_sum_3 out_3 +1 1 + +.end diff --git a/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.v b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.v new file mode 100644 index 000000000..5bf5ce5c8 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/micro_benchmark/test_mode_low.v @@ -0,0 +1,53 @@ +////////////////////////////////////// +// // +// 2x2 Test-modes Low density // +// // +////////////////////////////////////// + + +module test_mode_low ( + a, + b, + clk, + reset, + out ); + + input wire a; + input wire b; + input wire clk; + input wire reset; + output wire[3:0] out; + + reg[1:0] pipe_a; + reg[1:0] pipe_b; + reg[3:0] pipe_sum; + wire[7:0] sum; + + assign sum[1:0] = pipe_a[1] + pipe_b[1] + sum[7]; + assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2]; + assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3]; + assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0]; + assign out = pipe_sum; + + initial begin + pipe_a <= 2'b00; + pipe_b <= 2'b00; + pipe_sum <= 4'b0000; + end + + always @(posedge clk or posedge reset) begin + if(rst) begin + pipe_a <= 2'b00; + pipe_b <= 2'b00; + pipe_b[1] <= pipe_b[0]; + pipe_sum <= 4'b0000; + end else begin + pipe_a[0] <= a; + pipe_a[1] <= pipe_a[0]; + pipe_b[0] <= b; + pipe_b[1] <= pipe_b[0]; + pipe_sum <= {sum[6], sum[4], sum[2], sum[0]}; + end + end + +endmodule diff --git a/openfpga_flow/tasks/decoder_2_4/run.openfpga b/openfpga_flow/tasks/decoder_2_4/run.openfpga new file mode 100755 index 000000000..febc53dc8 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/run.openfpga @@ -0,0 +1,61 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 20 + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v b/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v new file mode 100755 index 000000000..dc4c3eb01 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v @@ -0,0 +1,73 @@ +`timescale 1ns/1ps + +module CCFFX1 ( // need to look deeper, we should have a reset signal!! + input D, + input CK, + input R, + output Q, + output QB); + + DFFRPQ_X1N_A9PP84TR_C14 DFFRPQ_X1N_A9PP84TR_C14_0 (.D(D), .Q(Q), .CK(CK), .R(R)); + INV_X1N_A9PP84TR_C14 INV_X1N_A9PP84TR_C14_0 (.A(Q), .Y(QB)); +endmodule + +module GPIO ( + output A, + output IE, + output OE, + input Y, // The output that is z + input in, + output out, + input mem_out); + + assign A = in; + assign out = Y; // it is assign as if it was an input but it is not. + assign IE = mem_out; + INV_X1N_A9PP84TR_C14 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); + +endmodule + +module dpram ( + input clk, + input wen, + input ren, + input[9:0] waddr, + input[9:0] raddr, + input[31:0] d_in, + output[31:0] d_out ); + + wire LOW, HIGH; + wire n_ren, n_wen; + + TIELO_X1N_A9PP84TR_C14 Llevel ( + .Y (LOW) ); + + TIEHI_X1N_A9PP84TR_C14 Hlevel ( + .Y (HIGH) ); + + INV_X1N_A9PP84TR_C14 inv_ren ( + .A (ren), + .Y (n_ren) ); + + INV_X1N_A9PP84TR_C14 inv_wen ( + .A (wen), + .Y (n_wen) ); + + mem32x1024MW4_B4 memory_0 ( + .CLKA (clk), // Reading Port + .CENA (n_ren), + .AA (raddr), + .QA (d_out), + .DB (d_in), //Writing port + .CLKB (clk), + .CENB (n_wen), + .AB (waddr), + .STOV (LOW), //Self-Time Override -> for test -> should be set to zero + .EMAA ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port A -> can slow down pulses if not set to zero + .EMASA (LOW), // = 0 if STOV = 0 + .EMAB ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port B -> can slow down pulses if not set to zero => default value is 2 + .RET1N (HIGH) ); //Retention, active low + +endmodule diff --git a/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v.bak b/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v.bak new file mode 100755 index 000000000..0c3d38457 --- /dev/null +++ b/openfpga_flow/tasks/decoder_2_4/sc_verilog/std_cell_extract.v.bak @@ -0,0 +1,73 @@ +`timescale 1ns/1ps + +module CCFFX1 ( // need to look deeper, we should have a reset signal!! + input D, + input CK, + input R, + output Q, + output QB); + + DFFRPQ_X1N_A9PP84TR_C14 DFFRPQ_X1N_A9PP84TR_C14_0 (.D(D), .Q(Q), .CK(CK), .R(R)); + INV_X1N_A9PP84TR_C14 INV_X1N_A9PP84TR_C14_0 (.A(Q), .Y(QB)); +endmodule + +module GPIO ( + output A, + output IE, + output OE, + output Y, + input in, + output out, + input mem_out); + + assign A = in; + assign out = Y; + assign IE = mem_out; + INV_X1N_A9PP84TR_C14 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); + +endmodule + +module dpram ( + input clk, + input wen, + input ren, + input[9:0] waddr, + input[9:0] raddr, + input[31:0] d_in, + output[31:0] d_out ); + + wire LOW, HIGH; + wire n_ren, n_wen; + + TIELO_X1N_A9PP84TR_C14 Llevel ( + .Y (LOW) ); + + TIEHI_X1N_A9PP84TR_C14 Hlevel ( + .Y (HIGH) ); + + INV_X1N_A9PP84TR_C14 inv_ren ( + .A (ren), + .Y (n_ren) ); + + INV_X1N_A9PP84TR_C14 inv_wen ( + .A (wen), + .Y (n_wen) ); + + mem32x1024MW4_B4 memory_0 ( + .CLKA (clk), // Reading Port + .CENA (n_ren), + .AA (raddr), + .QA (d_out), + .DB (d_in), //Writing port + .CLKB (clk), + .CENB (n_wen), + .AB (waddr), + .STOV (LOW), //Self-Time Override -> for test -> should be set to zero + .EMAA ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port A -> can slow down pulses if not set to zero + .EMASA (LOW), // = 0 if STOV = 0 + .EMAB ({LOW, HIGH, LOW}), //Extra Margin Adjustment for port B -> can slow down pulses if not set to zero => default value is 2 + .RET1N (HIGH) ); //Retention, active low + +endmodule