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[Test] Add QoR csv file for vtr benchmarks

This commit is contained in:
tangxifan 2021-03-23 11:15:02 -06:00
parent 23e7f7f1f5
commit 351dec5935
2 changed files with 34 additions and 0 deletions
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6
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv Normal file
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##########################################################
# Metrics to check for VTR benchmark bitstream generation
##########################################################
metric
mult_blocks
memory_blocks
1 ##########################################################
2 # Metrics to check for VTR benchmark bitstream generation
3 ##########################################################
4 metric
5 mult_blocks
6 memory_blocks

28
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv Normal file
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#####################################################################
# A database of benchmarks to be checked
# Reference: https://janders.eecg.utoronto.ca/pdfs/p77-rose.pdf
# Name,number of multipliers,number of RAMs
# IMPORTANT:
# - the name is tuned due to the naming convention of openfpga task-run script
# - the limitation should be CHANGED!!!
#####################################################################
name,mult_blocks,memory_blocks
00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0
00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0
00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1
00_memset_MIN_ROUTE_CHAN_WIDTH,0,1
00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0
00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0
00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9
00_LU32PEEng_MIN_ROUTE_CHAN_WIDTH,32,9
00_mcml_MIN_ROUTE_CHAN_WIDTH,30,10
00_mkDelayWorker32B_MIN_ROUTE_CHAN_WIDTH,0,9
00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3
00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3
00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2
00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1
00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0
00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0
00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0
00_sv_chip2_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,564,0
00_sv_chip3_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0
1 #####################################################################
2 # A database of benchmarks to be checked
3 # Reference: https://janders.eecg.utoronto.ca/pdfs/p77-rose.pdf
4 # Name,number of multipliers,number of RAMs
5 # IMPORTANT:
6 # - the name is tuned due to the naming convention of openfpga task-run script
7 # - the limitation should be CHANGED!!!
8 #####################################################################
9 name,mult_blocks,memory_blocks
10 00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0
11 00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0
12 00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1
13 00_memset_MIN_ROUTE_CHAN_WIDTH,0,1
14 00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0
15 00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0
16 00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9
17 00_LU32PEEng_MIN_ROUTE_CHAN_WIDTH,32,9
18 00_mcml_MIN_ROUTE_CHAN_WIDTH,30,10
19 00_mkDelayWorker32B_MIN_ROUTE_CHAN_WIDTH,0,9
20 00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3
21 00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3
22 00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2
23 00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1
24 00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0
25 00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0
26 00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0
27 00_sv_chip2_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,564,0
28 00_sv_chip3_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0