diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv new file mode 100644 index 000000000..80ebbc544 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv @@ -0,0 +1,6 @@ +########################################################## +# Metrics to check for VTR benchmark bitstream generation +########################################################## +metric +mult_blocks +memory_blocks diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv new file mode 100644 index 000000000..af8842eed --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv @@ -0,0 +1,28 @@ +##################################################################### +# A database of benchmarks to be checked +# Reference: https://janders.eecg.utoronto.ca/pdfs/p77-rose.pdf +# Name,number of multipliers,number of RAMs +# IMPORTANT: +# - the name is tuned due to the naming convention of openfpga task-run script +# - the limitation should be CHANGED!!! +##################################################################### +name,mult_blocks,memory_blocks +00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0 +00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0 +00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1 +00_memset_MIN_ROUTE_CHAN_WIDTH,0,1 +00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0 +00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0 +00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9 +00_LU32PEEng_MIN_ROUTE_CHAN_WIDTH,32,9 +00_mcml_MIN_ROUTE_CHAN_WIDTH,30,10 +00_mkDelayWorker32B_MIN_ROUTE_CHAN_WIDTH,0,9 +00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3 +00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3 +00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2 +00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1 +00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0 +00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0 +00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0 +00_sv_chip2_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,564,0 +00_sv_chip3_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0