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[arch] fixed a bug which caused verification failed

This commit is contained in:
tangxifan 2022-10-13 15:33:43 -07:00
parent 31da9bf6ea
commit 33e2b16cb1
1 changed files with 2 additions and 0 deletions
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openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml
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@ -202,9 +202,11 @@
<tile_annotations> <tile_annotations>
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0"> <global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/> <tile name="clb" port="clk"/>
<tile name="io" port="clk"/>
</global_port> </global_port>
<global_port name="op_reset" is_reset="true" default_val="0"> <global_port name="op_reset" is_reset="true" default_val="0">
<tile name="clb" port="reset"/> <tile name="clb" port="reset"/>
<tile name="io" port="reset"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>