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[core] fixed the bug

This commit is contained in:
tangxifan 2024-09-20 22:20:41 -07:00
parent 6551ca81e5
commit 33a253da3d
2 changed files with 27 additions and 3 deletions
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28
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -440,8 +440,20 @@ static int rec_expand_and_route_clock_spine(
* global net is mapped to the internal driver, use it as the previous
* node */
size_t use_int_driver = 0;
if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() &&
vtr::Point<int> int_driver_coord(des_coord.x(), des_coord.y());
if (des_spine_direction == Direction::INC &&
clk_ntwk.spine_track_type(curr_spine) == CHANX) {
int_driver_coord.set_x(des_coord.x() - 1);
}
if (des_spine_direction == Direction::INC &&
clk_ntwk.spine_track_type(curr_spine) == CHANY) {
int_driver_coord.set_y(des_coord.y() - 1);
}
if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() &&
tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n",
des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str());
for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) {
RRNodeId opin_node = rr_graph.edge_src_node(cand_edge);
if (OPIN != rr_graph.node_type(opin_node)) {
@ -501,8 +513,20 @@ static int rec_expand_and_route_clock_spine(
* global net is mapped to the internal driver, use it as the previous
* node */
size_t use_int_driver = 0;
if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() &&
vtr::Point<int> int_driver_coord(des_coord.x(), des_coord.y());
if (des_spine_direction == Direction::INC &&
clk_ntwk.spine_track_type(curr_spine) == CHANX) {
int_driver_coord.set_x(des_coord.x() - 1);
}
if (des_spine_direction == Direction::INC &&
clk_ntwk.spine_track_type(curr_spine) == CHANY) {
int_driver_coord.set_y(des_coord.y() - 1);
}
if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() &&
tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n",
des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str());
for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) {
RRNodeId opin_node = rr_graph.edge_src_node(cand_edge);
if (OPIN != rr_graph.node_type(opin_node)) {

2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml
View File

@ -6,7 +6,7 @@
</partition>
<partition name="int_clk_part">
<add_atom name_pattern="int_clk*"/>
<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
</partition>
</partition_list>
</vpr_constraints>