From 33a253da3dcd72a16670375e11192e1e0195cb3e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Sep 2024 22:20:41 -0700
Subject: [PATCH] [core] fixed the bug

---
 .../src/annotation/route_clock_rr_graph.cpp   | 28 +++++++++++++++++--
 .../config/vpr_constraint_clk_cond.xml        |  2 +-
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp
index e60da7fb3..fe5e6a9fc 100644
--- a/openfpga/src/annotation/route_clock_rr_graph.cpp
+++ b/openfpga/src/annotation/route_clock_rr_graph.cpp
@@ -440,8 +440,20 @@ static int rec_expand_and_route_clock_spine(
        * global net is mapped to the internal driver, use it as the previous
        * node  */
       size_t use_int_driver = 0;
-      if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() &&
+      vtr::Point<int> int_driver_coord(des_coord.x(), des_coord.y());
+      if (des_spine_direction == Direction::INC &&
+          clk_ntwk.spine_track_type(curr_spine) == CHANX) {
+        int_driver_coord.set_x(des_coord.x() - 1);
+      }
+      if (des_spine_direction == Direction::INC &&
+          clk_ntwk.spine_track_type(curr_spine) == CHANY) {
+        int_driver_coord.set_y(des_coord.y() - 1);
+      }
+
+      if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() &&
           tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
+        VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n",
+                 des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str());
         for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) {
           RRNodeId opin_node = rr_graph.edge_src_node(cand_edge);
           if (OPIN != rr_graph.node_type(opin_node)) {
@@ -501,8 +513,20 @@ static int rec_expand_and_route_clock_spine(
      * global net is mapped to the internal driver, use it as the previous
      * node  */
     size_t use_int_driver = 0;
-    if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() &&
+    vtr::Point<int> int_driver_coord(des_coord.x(), des_coord.y());
+    if (des_spine_direction == Direction::INC &&
+        clk_ntwk.spine_track_type(curr_spine) == CHANX) {
+      int_driver_coord.set_x(des_coord.x() - 1);
+    }
+    if (des_spine_direction == Direction::INC &&
+        clk_ntwk.spine_track_type(curr_spine) == CHANY) {
+      int_driver_coord.set_y(des_coord.y() - 1);
+    }
+
+    if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() &&
         tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
+      VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n",
+               des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str());
       for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) {
         RRNodeId opin_node = rr_graph.edge_src_node(cand_edge);
         if (OPIN != rr_graph.node_type(opin_node)) {
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml
index b80e7299c..f7a7dccd5 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml
@@ -6,7 +6,7 @@
     </partition>
     <partition name="int_clk_part">
       <add_atom name_pattern="int_clk*"/>
-      <add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
+      <add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
     </partition>
   </partition_list>
 </vpr_constraints>