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bug fixing in Verilog top-level testbench generation

This commit is contained in:
tangxifan 2020-04-05 17:50:11 -06:00
parent decc1dc4b2
commit 3369d724e9
1 changed files with 12 additions and 0 deletions
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12
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -353,6 +353,18 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIN_PORT)) {
fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
}
/* Add an empty line as a splitter */
fp << std::endl;
for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPOUT_PORT)) {
fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
}
/* Add an empty line as a splitter */
fp << std::endl;
/* Add local wires/registers that drive stimulus /* Add local wires/registers that drive stimulus
* We create these general purpose ports here, * We create these general purpose ports here,
* and then wire them to the ports of FPGA fabric depending on their usage * and then wire them to the ports of FPGA fabric depending on their usage