From 3369d724e9c9a066cb870aef38735ed171d48b0b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 Apr 2020 17:50:11 -0600 Subject: [PATCH] bug fixing in Verilog top-level testbench generation --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 95f88bf92..98d69c337 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -353,6 +353,18 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Add an empty line as a splitter */ fp << std::endl; + for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIN_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + + for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPOUT_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + /* Add local wires/registers that drive stimulus * We create these general purpose ports here, * and then wire them to the ports of FPGA fabric depending on their usage