clean up documentation build warnings and add guidelines for port naming

docs/source/arch_lang/circuit_model_examples.rst

@@ -231,7 +231,7 @@ SRAMs
 .. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
 
 Logic gates
------
+-----------
 
 .. code-block:: xml
 

docs/source/arch_lang/circuit_modules.rst

@@ -98,3 +98,5 @@ Transistor level
     * **is_config_enable:** can be either ``true`` or ``false``. Only valid when ``is_global`` is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
 
 .. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details.
+
+.. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``ccff_head`` and ``ccff_tail``.

docs/source/fpga_bitstream/index.rst

@@ -1,5 +1,5 @@
 FPGA-Bitstream
-=============
+==============
 
 .. _fpga_bitstream:
    User Manual for FPGA Bitstream Generator

docs/source/fpga_verilog/func_verify.rst

@@ -5,20 +5,8 @@ If the --fpga_verilog_print_modelsim_autodeck option is selected, it is possible
 
 The point of the verification step is to check that the FPGA reproduces the right function. As illustrated in :numref:`fig_ModelSim`, inside of the red rectangle is the programming of the FPGA. Each prog clock cycle corresponds to one bit added to the scan-chain. Inside of the blue rectangle, we see that the prog clock is set to 0 and the operating clock is toggled. Two outputs are shown, benchmark and FPGA, and by checking the value on both of them, we know if the functionality is respected.
 
-
-
-
-
 .. _fig_ModelSim:
 
 .. figure:: ./figures/Verification_step.pdf
    :scale: 100%
    :alt: Functional Verification using ModelSim
-
-
-
-
-
-
-
-

docs/source/z_reference.bib

@@ -14,19 +14,6 @@ doi={10.1109/ICCD.2015.7357183},
 ISSN={},
 month={Oct},}
 
-@ARTICLE{XTang_JETCAS_2018,
-author={X. Tang and E. Giacomin and G. De Micheli and P. Gaillardon},
-journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
-title={Post-P amp;R Performance and Power Analysis for RRAM-Based FPGAs},
-year={2018},
-volume={8},
-number={3},
-pages={639-650},
-keywords={Field programmable gate arrays;Random access memory;Analytical models;Delays;Resistance;Routing;Programmable logic arrays;resistive ram;simulation;system modeling;integrated circuit reliability},
-doi={10.1109/JETCAS.2018.2847600},
-ISSN={2156-3357},
-month={Sept},}
-
 @book{VBetz_Book_1999,
  editor = {Betz, Vaughn and Rose, Jonathan and Marquardt, Alexander},
  title = {Architecture and CAD for Deep-Submicron FPGAs},
@@ -36,31 +23,6 @@ month={Sept},}
  address = {Norwell, MA, USA},
 } 
 
-@article{XTang_TCAS1_2016,
-	title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}},
-	author={X. Tang and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
-	journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
-	volume={63},
-	number={4},
-	pages={503--516},
-	year={2016},
-	publisher={IEEE}
-}
-
-
-@ARTICLE{XTang_TCAS1_2017,
-	author={X. Tang and E. Giacomin and G. De Micheli and P. E. Gaillardon},
-	journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
-	title={{Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure}},
-	year={2017},
-	volume={64},
-	number={5},
-	pages={1173-1186},
-	keywords={Delays;Logic gates;Multiplexing;Programming;Resistance;Routing;Transistors;Circuit design;high-performance;low-power;multiplexer;resistive memory},
-	doi={10.1109/TCSI.2016.2638542},
-	ISSN={1549-8328},
-	month={May},}
-
 @inproceedings{JLuu_FPGA_2011,
 	author = {Luu, Jason and Anderson, Jason Helge and Rose, Jonathan Scott},
 	title = {{Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect}},