[core] now support add internal drivers to clock tree
This commit is contained in:
tangxifan
parent
272d78eb43
commit
31d4b4c402
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@ -389,6 +389,46 @@ std::vector<std::string> ClockNetwork::tree_flatten_taps(
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return flatten_taps;
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}
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std::vector<std::string> ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const {
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std::vector<std::string> flatten_taps;
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for (const std::string& tap_name : internal_driver_port(int_driver_id)) {
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StringToken tokenizer(tap_name);
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std::vector<std::string> pin_tokens = tokenizer.split(".");
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if (pin_tokens.size() != 2) {
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VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n",
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tap_name.c_str());
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exit(1);
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}
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PortParser tile_parser(pin_tokens[0]);
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BasicPort tile_info = tile_parser.port();
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PortParser pin_parser(pin_tokens[1]);
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BasicPort pin_info = pin_parser.port();
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if (!tile_info.is_valid()) {
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VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n",
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tap_name.c_str());
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exit(1);
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}
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if (!pin_info.is_valid()) {
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VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n",
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tap_name.c_str());
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exit(1);
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}
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for (size_t& tile_idx : tile_info.pins()) {
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std::string flatten_tile_str =
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tile_info.get_name() + "[" + std::to_string(tile_idx) + "]";
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for (size_t& pin_idx : pin_info.pins()) {
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if (pin_idx != size_t(clk_pin_id)) {
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continue;
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}
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std::string flatten_pin_str =
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pin_info.get_name() + "[" + std::to_string(pin_idx) + "]";
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flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str);
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}
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}
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}
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return flatten_taps;
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}
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ClockTreeId ClockNetwork::find_tree(const std::string& name) const {
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auto result = tree_name2id_map_.find(name);
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if (result == tree_name2id_map_.end()) {
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@ -125,6 +125,7 @@ class ClockNetwork {
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const ClockSpineId& spine_id,
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const ClockSwitchPointId& switch_point_id) const;
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std::string internal_driver_port(const ClockInternalDriverId& int_driver_id) const;
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std::vector<std::string> flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const;
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/* Return the original list of tap pins that is in storage; useful for parsers
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*/
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@ -545,7 +545,7 @@ static void add_rr_graph_block_clock_edges(
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clk_ntwk.default_tap_switch(), false);
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edge_count++;
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}
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VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n",
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VTR_LOGV(verbose, "\tWill add %lu edges to IPINs\n",
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edge_count - curr_edge_count);
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}
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}
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@ -557,6 +557,147 @@ static void add_rr_graph_block_clock_edges(
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num_edges_to_create += edge_count;
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}
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/********************************************************************
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* Try to find an OPIN of a grid which satisfy the requirement of clock pins
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* that has been defined in clock network. If the OPIN does exist in a
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* routing resource graph, add it to the node list
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*******************************************************************/
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static void try_find_and_add_clock_opin2track_node(
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std::vector<RRNodeId>& opin_nodes, const DeviceGrid& grids,
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const RRGraphView& rr_graph_view, const size_t& layer,
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const vtr::Point<size_t>& grid_coord, const e_side& pin_side,
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const ClockNetwork& clk_ntwk,
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const ClockInternalDriverId& int_driver_id) {
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t_physical_tile_type_ptr grid_type = grids.get_physical_type(
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t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
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for (std::string tap_pin_name :
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clk_ntwk.flatten_internal_driver_port(int_driver_id)) {
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/* tap pin name could be 'io[5:5].a2f[0]' */
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int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name);
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if (grid_pin_idx == grid_type->num_pins) {
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continue;
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}
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RRNodeId opin_node = rr_graph_view.node_lookup().find_node(
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layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side);
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if (rr_graph_view.valid_node(opin_node)) {
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opin_nodes.push_back(opin_node);
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}
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}
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}
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/********************************************************************
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* Find the source OPIN nodes as internal drivers for a clock node
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* For example
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* clk0_lvl1_chany[1][1]
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* ^
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* |
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* internal_driver OPIN[0] -->-------+
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* ^
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* |
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* internal_driver OPIN[1]
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*
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* Coordinate system:
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*
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* +----------+----------+------------+
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* | Grid | CBy | Grid |
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* | [x][y+1] | [x][y+1] | [x+1][y+1] |
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* +----------+----------+------------+
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* | CBx | SB | CBx |
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* | [x][y] | [x][y] | [x+1][y] |
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* +----------+----------+------------+
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* | Grid | CBy | Grid |
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* | [x][y] | [x][y] | [x+1][y] |
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* +----------+----------+------------+
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*******************************************************************/
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static std::vector<RRNodeId> find_clock_opin2track_node(
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const DeviceGrid& grids, const RRGraphView& rr_graph_view,
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const size_t& layer,
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const vtr::Point<int>& sb_coord,
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const ClockNetwork& clk_ntwk,
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const std::vector<ClockInternalDriverId>& int_driver_ids
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) {
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std::vector<RRNodeId> opin_nodes;
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/* Find opins from
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* - Grid[x][y+1] on right and bottom sides
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* - Grid[x+1][y+1] on left and bottom sides
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* - Grid[x][y] on right and top sides
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* - Grid[x+1][y] on left and top sides
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*/
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std::array<vtr::Point<int>, 4> grid_coords;
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std::array<std::array<e_side>, 2>, 4> grid_sides;
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grid_coords[0] = grid_coord(sb_coord.x(), sb_coord.y() + 1);
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grid_sides[0] = {RIGHT, BOTTOM};
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grid_coords[1] = grid_coord(sb_coord.x() + 1, sb_coord.y() + 1);
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grid_sides[1] = {LEFT, BOTTOM};
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grid_coords[2] = grid_coord(sb_coord.x() + 1, sb_coord.y());
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grid_sides[2] = {RIGHT, TOP};
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grid_coords[3] = grid_coord(sb_coord.x(), sb_coord.y());
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grid_sides[3] = {LEFT, TOP};
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for (size_t igrid = 0; igrid < 4; igrid++) {
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vtr::Point<int> grid_coord = grid_coords[igrid];
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for (e_side grid_side : grid_sides[igrid]) {
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for (ClockInternalDriverId int_driver_id : int_driver_ids) {
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try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view,
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layer, grid_coord, grid_side,
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clk_ntwk, int_driver_id);
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}
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}
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}
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return opin_nodes;
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}
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/********************************************************************
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* Add edges between OPIN of programmable blocks and clock routing tracks
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* Note that such edges only occur at the switching points of spines
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* Different from add_rr_graph_block_clock_edges(), we follow the clock spines here
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* By expanding on switching points, internal drivers will be added
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*******************************************************************/
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static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
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const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
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const DeviceGrid& grids, const size_t& layer,
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const ClockNetwork& clk_ntwk, const bool& verbose) {
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size_t edge_count = 0;
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for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) {
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VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n",
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clk_ntwk.spine_name(ispine).c_str());
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for (auto ipin : clk_ntwk.pins(clk_tree)) {
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for (ClockSwitchPointId switch_point_id :
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clk_ntwk.spine_switch_points(ispine)) {
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if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) {
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continue; /* We only focus on switching points containing internal drivers */
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}
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size_t curr_edge_count = edge_count;
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/* Get the rr node of destination spine */
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ClockSpineId des_spine =
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clk_ntwk.spine_switch_point_tap(ispine, switch_point_id);
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vtr::Point<int> des_coord = clk_ntwk.spine_start_point(des_spine);
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Direction des_spine_direction = clk_ntwk.spine_direction(des_spine);
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ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine);
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RRNodeId des_node =
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clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
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des_spine_level, ipin, des_spine_direction);
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/* Walk through each qualified OPIN, build edges */
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vtr::Point<int> src_coord =
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clk_ntwk.spine_switch_point(ispine, switch_point_id);
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std::vector<ClockInternalDriverId> int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id);
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for (RRNodId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) {
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/* Create edges */
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VTR_ASSERT(rr_graph_view.valid_node(des_node));
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rr_graph_builder.create_edge(src_node, des_node,
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clk_ntwk.default_driver_switch(), false);
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edge_count++;
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}
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VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n",
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edge_count - curr_edge_count, des_coord.x(), des_coord.y());
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}
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}
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}
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/* Allocate edges */
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rr_graph_builder.build_edges(true);
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num_edges_to_create += edge_count;
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Add edges to interconnect clock nodes
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* Walk through the routing tracks in each connection block (driver nodes)
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@ -614,6 +755,8 @@ static void add_rr_graph_clock_edges(
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clk_ntwk, chany_coord, CHANY, verbose);
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}
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}
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/* Add edges between OPIN (internal driver) and clock routing tracks */
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add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, rr_graph_view, grids, layer, clk_ntwk, verbose);
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}
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/********************************************************************
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