Merge pull request #1128 from lnis-uofu/vtr_upgrade

Upgrade VTR to latest version in its 'openfpga' branch

.github/workflows/build.yml

@@ -36,10 +36,10 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           fetch-depth: 0
-          submodules: true
+
       - name: Check for source code changes
         id: changes
         run: |
@@ -114,9 +114,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install dependencies
         run: sudo bash ./.github/workflows/install_dependencies_build.sh
@@ -129,10 +127,15 @@ jobs:
 
       - uses: hendrikmuhs/ccache-action@v1
 
+      - name: checkout submodules
+        shell: bash
+        run: |
+          make checkout
+
       - name: Build
         shell: bash
         run: |
-          make all BUILD_TYPE=$BUILD_TYPE
+          make compile BUILD_TYPE=$BUILD_TYPE
 
       # Check the cache size and see if it is over the limit
       - name: Check ccache size
@@ -200,9 +203,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install dependencies
         run: sudo bash ./.github/workflows/install_dependencies_build.sh
@@ -215,10 +216,15 @@ jobs:
 
       - uses: hendrikmuhs/ccache-action@v1
 
+      - name: checkout submodules
+        shell: bash
+        run: |
+          make checkout
+
       - name: Build
         shell: bash
         run: |
-          make all BUILD_TYPE=$BUILD_TYPE CMAKE_FLAGS="${{ matrix.config.cmake_flags }}"
+          make compile BUILD_TYPE=$BUILD_TYPE CMAKE_FLAGS="${{ matrix.config.cmake_flags }}"
 
   ubuntu_support:
     needs: change_detect
@@ -243,9 +249,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install dependencies
         run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh
@@ -258,10 +262,15 @@ jobs:
 
       - uses: hendrikmuhs/ccache-action@v1
 
+      - name: checkout submodules
+        shell: bash
+        run: |
+          make checkout
+
       - name: Build
         shell: bash
         run: |
-          make all BUILD_TYPE=$BUILD_TYPE 
+          make compile BUILD_TYPE=$BUILD_TYPE 
 
   debug_build:
     needs: change_detect
@@ -290,9 +299,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install dependencies
         run: |
@@ -308,10 +315,15 @@ jobs:
 
       - uses: hendrikmuhs/ccache-action@v1
 
+      - name: checkout submodules
+        shell: bash
+        run: |
+          make checkout
+
       - name: Build
         shell: bash
         run: |
-          make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }}
+          make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }}
 
       - name: Quick Test
         shell: bash
@@ -343,9 +355,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install dependencies
         run: |
@@ -361,10 +371,15 @@ jobs:
 
       - uses: hendrikmuhs/ccache-action@v1
 
+      - name: checkout submodules
+        shell: bash
+        run: |
+          make checkout
+
       - name: Build
         shell: bash
         run: |
-          make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON"
+          make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON"
 
       - name: Quick Test
         shell: bash
@@ -382,7 +397,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
       - name: Download a built artifacts
         uses: actions/download-artifact@v2
         with:
@@ -435,7 +450,7 @@ jobs:
           access_token: ${{ github.token }}
     
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
       - name: Download a built artifacts
         uses: actions/download-artifact@v2
         with:
@@ -493,9 +508,8 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
+
-          submodules: true
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04)
         shell: bash
         run: |

.github/workflows/cell_lib_test.yml

@@ -21,9 +21,7 @@ jobs:
           access_token: ${{ github.token }}
           
       - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
-        with:
-          submodules: true
 
       - name: Install Dependencies
         run: |

CMakeLists.txt

@@ -81,8 +81,10 @@ set(ODIN_COVERAGE OFF CACHE BOOL "Enable building odin with coverage flags in Ve
 set(ODIN_TIDY OFF CACHE BOOL "Enable building odin with clang tidy in Verilog-to-Routing")
 set(ODIN_SANITIZE OFF CACHE BOOL "Enable building odin with sanitize flags in Verilog-to-Routing")
 set(WITH_YOSYS OFF CACHE BOOL "Enable building Yosys in Verilog-to-Routing")
+set(WITH_PARMYS OFF CACHE BOOL "Enable Yosys as elaborator and parmys-plugin as partial mapper")
 set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Routing")
 set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
+set(YOSYS_F4PGA_PLUGINS OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins")
 set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
 # TODO: OpenFPGA and VPR has different requirements on no-warning build, e.g., on OS and compiler versions
 #set(VTR_ENABLE_STRICT_COMPILE ${OPENFPGA_ENABLE_STRICT_COMPILE} CACHE BOOL "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)")

Makefile

@@ -58,7 +58,7 @@ help:
 checkout: 
 # Update all the submodules
 	git submodule init
-	git submodule update --init --recursive
+	git submodule update --init --depth 1
 
 prebuild:
 # Run cmake to generate Makefile under the build directory, before compilation

openfpga/src/annotation/annotate_simulation_setting.cpp

@@ -208,14 +208,15 @@ int annotate_simulation_setting(
      *   - MUST mention in documentation that VPR should be run in timing
      * enabled mode
      */
-    ClbNetPinsMatrix<float> net_delay =
+    NetPinsMatrix<float> net_delay =
-      make_net_pins_matrix<float>(cluster_ctx.clb_nlist);
+      make_net_pins_matrix<float>((const Netlist<>&)cluster_ctx.clb_nlist);
     /* Load the net delays */
-    load_net_delay_from_routing(net_delay);
+    load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist,
+                                net_delay, false);
 
     /* Do final timing analysis */
     auto analysis_delay_calc = std::make_shared<AnalysisDelayCalculator>(
-      atom_ctx.nlist, atom_ctx.lookup, net_delay);
+      atom_ctx.nlist, atom_ctx.lookup, net_delay, false);
     auto timing_info = make_setup_hold_timing_info(analysis_delay_calc,
                                                    e_timing_update_type::FULL);
     timing_info->update();

openfpga/src/annotation/openfpga_annotate_routing.cpp

@@ -22,12 +22,14 @@ void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
                                const RoutingContext& routing_ctx,
                                VprRoutingAnnotation& vpr_routing_annotation,
                                const bool& verbose) {
-  vtr::vector<RRNodeId, ClusterNetId> node2net = annotate_rr_node_nets(
+  vtr::vector<RRNodeId, ParentNetId> node2net =
-    device_ctx, clustering_ctx, routing_ctx, verbose, false);
+    annotate_rr_node_nets((const Netlist<>&)clustering_ctx.clb_nlist,
+                          device_ctx, routing_ctx, verbose, false);
   for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes();
        ++node_id) {
-    vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id),
+    vpr_routing_annotation.set_rr_node_net(
-                                           node2net[RRNodeId(node_id)]);
+      RRNodeId(node_id),
+      convert_to_cluster_net_id(node2net[RRNodeId(node_id)]));
   }
   VTR_LOG("Loaded node-to-net mapping\n");
 }

openfpga/src/mux_lib/mux_library_builder.cpp

@@ -56,7 +56,7 @@ static void build_routing_arch_mux_library(
         if (CircuitModelId::INVALID() == rr_switch_circuit_model) {
           VTR_LOG_ERROR(
             "Unable to find the circuit model for rr_switch '%s'!\n",
-            rr_graph.rr_switch_inf(driver_switches[0]).name);
+            rr_graph.rr_switch_inf(driver_switches[0]).name.c_str());
           VTR_LOG("Node type: %s\n", rr_graph.node_type_string(node));
           VTR_LOG("Node coordinate: %s\n",
                   rr_graph.node_coordinate_to_string(node).c_str());

openfpga/src/vpr_wrapper/vpr_main.cpp

@@ -118,16 +118,20 @@ static int vpr_standalone(int argc, char** argv) {
 
     /* Read options, architecture, and circuit netlist */
     vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, &Arch);
+    const Netlist<>& net_list =
+      vpr_setup.RouterOpts.flat_routing
+        ? (const Netlist<>&)g_vpr_ctx.atom().nlist
+        : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
 
     if (Options.show_version) {
-      vpr_free_all(Arch, vpr_setup);
+      vpr_free_all(net_list, Arch, vpr_setup);
       return SUCCESS_EXIT_CODE;
     }
 
     bool flow_succeeded = vpr_flow(vpr_setup, Arch);
     if (!flow_succeeded) {
       VTR_LOG("VPR failed to implement circuit\n");
-      vpr_free_all(Arch, vpr_setup);
+      vpr_free_all(net_list, Arch, vpr_setup);
       return UNIMPLEMENTABLE_EXIT_CODE;
     }
 
@@ -135,31 +139,43 @@ static int vpr_standalone(int argc, char** argv) {
     print_timing_stats("Flow", timing_ctx.stats);
 
     /* free data structures */
-    vpr_free_all(Arch, vpr_setup);
+    vpr_free_all(net_list, Arch, vpr_setup);
 
     VTR_LOG("VPR succeeded\n");
 
   } catch (const tatum::Error& tatum_error) {
     VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str());
-    vpr_free_all(Arch, vpr_setup);
+    const Netlist<>& net_list =
+      vpr_setup.RouterOpts.flat_routing
+        ? (const Netlist<>&)g_vpr_ctx.atom().nlist
+        : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
+    vpr_free_all(net_list, Arch, vpr_setup);
 
     return ERROR_EXIT_CODE;
 
   } catch (const VprError& vpr_error) {
     vpr_print_error(vpr_error);
+    const Netlist<>& net_list =
+      vpr_setup.RouterOpts.flat_routing
+        ? (const Netlist<>&)g_vpr_ctx.atom().nlist
+        : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
 
     if (vpr_error.type() == VPR_ERROR_INTERRUPTED) {
-      vpr_free_all(Arch, vpr_setup);
+      vpr_free_all(net_list, Arch, vpr_setup);
       return INTERRUPTED_EXIT_CODE;
     } else {
-      vpr_free_all(Arch, vpr_setup);
+      vpr_free_all(net_list, Arch, vpr_setup);
       return ERROR_EXIT_CODE;
     }
 
   } catch (const vtr::VtrError& vtr_error) {
     VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(),
                   vtr_error.what());
-    vpr_free_all(Arch, vpr_setup);
+    const Netlist<>& net_list =
+      vpr_setup.RouterOpts.flat_routing
+        ? (const Netlist<>&)g_vpr_ctx.atom().nlist
+        : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
+    vpr_free_all(net_list, Arch, vpr_setup);
 
     return ERROR_EXIT_CODE;
   }

vtr-verilog-to-routing

@@ -1 +1 @@
-Subproject commit 9e53e9a0a7c18ba9a16ea08678da726b98c669d4
+Subproject commit d70659f424425dbaa6ecdb6dea40bf1841f02dac