From 817015f7b6ff6aab3094c9c6dccb76b6b8b85cd5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 16:46:43 +0800 Subject: [PATCH 01/12] [core] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 9e53e9a0a..d70659f42 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 9e53e9a0a7c18ba9a16ea08678da726b98c669d4 +Subproject commit d70659f424425dbaa6ecdb6dea40bf1841f02dac From 7f96d98083e6ccc747f366dca0d5d22de65585e5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 16:49:31 +0800 Subject: [PATCH 02/12] [ci] now git checkout does not download submodule; It is done by make checkout --- .github/workflows/build.yml | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e5223f0fe..505dd7fa2 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -37,9 +37,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - fetch-depth: 0 - submodules: true + - name: Check for source code changes id: changes run: | @@ -115,8 +113,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build.sh @@ -201,8 +197,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build.sh @@ -244,8 +238,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh @@ -291,8 +283,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install dependencies run: | @@ -344,8 +334,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install dependencies run: | @@ -494,8 +482,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true + - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04) shell: bash run: | From ae46442e8c8901946cdad5ff6aa012c19e1379c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 16:52:20 +0800 Subject: [PATCH 03/12] [script] now make checkout only checkout submodule by 1 depth --- Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9774e7863..49f6a0a73 100644 --- a/Makefile +++ b/Makefile @@ -58,7 +58,7 @@ help: checkout: # Update all the submodules git submodule init - git submodule update --init --recursive + git submodule update --init --depth 1 prebuild: # Run cmake to generate Makefile under the build directory, before compilation @@ -79,8 +79,9 @@ list_cmake_targets: prebuild # Show the targets available to be built, which can be specified through ``CMAKE_GOALS`` when compile cd ${BUILD_DIR} && make help && cd - -all: checkout compile +all: checkout # A shortcut command to run checkout and compile in serial + make compile CMAKE_GOALS=${CMAKE_GOALS} format-cpp: # Format all the C/C++ files under this project, excluding submodules From 9e50b2d923d5f1812e891a2715fb1a30d13d96fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 17:13:21 +0800 Subject: [PATCH 04/12] [ci] disable checkout submodules for cell library tests --- .github/workflows/cell_lib_test.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 5016297d5..9825fddfc 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -22,8 +22,6 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 - with: - submodules: true - name: Install Dependencies run: | From 691a6b2b734e5ff7d2327cda3926ea6dac8693fe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 17:19:07 +0800 Subject: [PATCH 05/12] [ci] now checkout all the branches and tags when detecting code changes --- .github/workflows/build.yml | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 505dd7fa2..e0cd7bc71 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -36,7 +36,9 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 + with: + fetch-depth: 0 - name: Check for source code changes id: changes @@ -112,7 +114,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build.sh @@ -196,7 +198,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build.sh @@ -237,7 +239,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install dependencies run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh @@ -282,7 +284,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install dependencies run: | @@ -333,7 +335,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install dependencies run: | @@ -370,7 +372,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Download a built artifacts uses: actions/download-artifact@v2 with: @@ -423,7 +425,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Download a built artifacts uses: actions/download-artifact@v2 with: @@ -481,7 +483,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04) shell: bash From 3780ca5150ed932d13cd24aaaa5a3c688cfb3b09 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 17:20:39 +0800 Subject: [PATCH 06/12] [ci] now all use checkout v3 --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 9825fddfc..619dc5251 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -21,7 +21,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Install Dependencies run: | From ffca43266fe6350fdcc221e33332732e4783f7c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 18 Apr 2023 17:35:59 +0800 Subject: [PATCH 07/12] [script] now disable yosys and parmys in vtr --- CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 35a2296c7..c3fc2cce6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -81,8 +81,10 @@ set(ODIN_COVERAGE OFF CACHE BOOL "Enable building odin with coverage flags in Ve set(ODIN_TIDY OFF CACHE BOOL "Enable building odin with clang tidy in Verilog-to-Routing") set(ODIN_SANITIZE OFF CACHE BOOL "Enable building odin with sanitize flags in Verilog-to-Routing") set(WITH_YOSYS OFF CACHE BOOL "Enable building Yosys in Verilog-to-Routing") +set(WITH_PARMYS OFF CACHE BOOL "Enable Yosys as elaborator and parmys-plugin as partial mapper") set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Routing") set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing") +set(YOSYS_F4PGA_PLUGINS OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins") set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number") # TODO: OpenFPGA and VPR has different requirements on no-warning build, e.g., on OS and compiler versions #set(VTR_ENABLE_STRICT_COMPILE ${OPENFPGA_ENABLE_STRICT_COMPILE} CACHE BOOL "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)") From a84cc52d7c7d7a7ee9072c62ff76b8c86e5c3ae8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Apr 2023 11:08:18 +0800 Subject: [PATCH 08/12] [core] fixed a few bugs due to the changes in vtr regarding flat router --- .../annotation/annotate_simulation_setting.cpp | 8 ++++---- .../annotation/openfpga_annotate_routing.cpp | 6 +++--- openfpga/src/vpr_wrapper/vpr_main.cpp | 18 +++++++++++------- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp index a3d489efe..08a06c2be 100644 --- a/openfpga/src/annotation/annotate_simulation_setting.cpp +++ b/openfpga/src/annotation/annotate_simulation_setting.cpp @@ -208,14 +208,14 @@ int annotate_simulation_setting( * - MUST mention in documentation that VPR should be run in timing * enabled mode */ - ClbNetPinsMatrix net_delay = - make_net_pins_matrix(cluster_ctx.clb_nlist); + NetPinsMatrix net_delay = + make_net_pins_matrix((const Netlist<>&)cluster_ctx.clb_nlist); /* Load the net delays */ - load_net_delay_from_routing(net_delay); + load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist, net_delay, false); /* Do final timing analysis */ auto analysis_delay_calc = std::make_shared( - atom_ctx.nlist, atom_ctx.lookup, net_delay); + atom_ctx.nlist, atom_ctx.lookup, net_delay, false); auto timing_info = make_setup_hold_timing_info(analysis_delay_calc, e_timing_update_type::FULL); timing_info->update(); diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 577106359..f5389f324 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -22,12 +22,12 @@ void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const RoutingContext& routing_ctx, VprRoutingAnnotation& vpr_routing_annotation, const bool& verbose) { - vtr::vector node2net = annotate_rr_node_nets( - device_ctx, clustering_ctx, routing_ctx, verbose, false); + vtr::vector node2net = annotate_rr_node_nets( + (const Netlist<>&)clustering_ctx.clb_nlist, device_ctx, routing_ctx, verbose, false); for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes(); ++node_id) { vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id), - node2net[RRNodeId(node_id)]); + convert_to_cluster_net_id(node2net[RRNodeId(node_id)])); } VTR_LOG("Loaded node-to-net mapping\n"); } diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp index cc6924b49..10b7a9ccd 100644 --- a/openfpga/src/vpr_wrapper/vpr_main.cpp +++ b/openfpga/src/vpr_wrapper/vpr_main.cpp @@ -118,16 +118,17 @@ static int vpr_standalone(int argc, char** argv) { /* Read options, architecture, and circuit netlist */ vpr_init(argc, const_cast(argv), &Options, &vpr_setup, &Arch); + const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (Options.show_version) { - vpr_free_all(Arch, vpr_setup); + vpr_free_all(net_list, Arch, vpr_setup); return SUCCESS_EXIT_CODE; } bool flow_succeeded = vpr_flow(vpr_setup, Arch); if (!flow_succeeded) { VTR_LOG("VPR failed to implement circuit\n"); - vpr_free_all(Arch, vpr_setup); + vpr_free_all(net_list, Arch, vpr_setup); return UNIMPLEMENTABLE_EXIT_CODE; } @@ -135,31 +136,34 @@ static int vpr_standalone(int argc, char** argv) { print_timing_stats("Flow", timing_ctx.stats); /* free data structures */ - vpr_free_all(Arch, vpr_setup); + vpr_free_all(net_list, Arch, vpr_setup); VTR_LOG("VPR succeeded\n"); } catch (const tatum::Error& tatum_error) { VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str()); - vpr_free_all(Arch, vpr_setup); + const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + vpr_free_all(net_list, Arch, vpr_setup); return ERROR_EXIT_CODE; } catch (const VprError& vpr_error) { vpr_print_error(vpr_error); + const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (vpr_error.type() == VPR_ERROR_INTERRUPTED) { - vpr_free_all(Arch, vpr_setup); + vpr_free_all(net_list, Arch, vpr_setup); return INTERRUPTED_EXIT_CODE; } else { - vpr_free_all(Arch, vpr_setup); + vpr_free_all(net_list, Arch, vpr_setup); return ERROR_EXIT_CODE; } } catch (const vtr::VtrError& vtr_error) { VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(), vtr_error.what()); - vpr_free_all(Arch, vpr_setup); + const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + vpr_free_all(net_list, Arch, vpr_setup); return ERROR_EXIT_CODE; } From cb4512b9255962dd0cd1c0c7b3956de00a6a89e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Apr 2023 11:10:42 +0800 Subject: [PATCH 09/12] [core] code format --- .../annotate_simulation_setting.cpp | 3 ++- .../annotation/openfpga_annotate_routing.cpp | 10 ++++++---- openfpga/src/vpr_wrapper/vpr_main.cpp | 20 +++++++++++++++---- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp index 08a06c2be..3c3c7b3ee 100644 --- a/openfpga/src/annotation/annotate_simulation_setting.cpp +++ b/openfpga/src/annotation/annotate_simulation_setting.cpp @@ -211,7 +211,8 @@ int annotate_simulation_setting( NetPinsMatrix net_delay = make_net_pins_matrix((const Netlist<>&)cluster_ctx.clb_nlist); /* Load the net delays */ - load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist, net_delay, false); + load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist, + net_delay, false); /* Do final timing analysis */ auto analysis_delay_calc = std::make_shared( diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index f5389f324..6c5327e04 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -22,12 +22,14 @@ void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const RoutingContext& routing_ctx, VprRoutingAnnotation& vpr_routing_annotation, const bool& verbose) { - vtr::vector node2net = annotate_rr_node_nets( - (const Netlist<>&)clustering_ctx.clb_nlist, device_ctx, routing_ctx, verbose, false); + vtr::vector node2net = + annotate_rr_node_nets((const Netlist<>&)clustering_ctx.clb_nlist, + device_ctx, routing_ctx, verbose, false); for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes(); ++node_id) { - vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id), - convert_to_cluster_net_id(node2net[RRNodeId(node_id)])); + vpr_routing_annotation.set_rr_node_net( + RRNodeId(node_id), + convert_to_cluster_net_id(node2net[RRNodeId(node_id)])); } VTR_LOG("Loaded node-to-net mapping\n"); } diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp index 10b7a9ccd..e9b5d563a 100644 --- a/openfpga/src/vpr_wrapper/vpr_main.cpp +++ b/openfpga/src/vpr_wrapper/vpr_main.cpp @@ -118,7 +118,10 @@ static int vpr_standalone(int argc, char** argv) { /* Read options, architecture, and circuit netlist */ vpr_init(argc, const_cast(argv), &Options, &vpr_setup, &Arch); - const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = + vpr_setup.RouterOpts.flat_routing + ? (const Netlist<>&)g_vpr_ctx.atom().nlist + : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (Options.show_version) { vpr_free_all(net_list, Arch, vpr_setup); @@ -142,14 +145,20 @@ static int vpr_standalone(int argc, char** argv) { } catch (const tatum::Error& tatum_error) { VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str()); - const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = + vpr_setup.RouterOpts.flat_routing + ? (const Netlist<>&)g_vpr_ctx.atom().nlist + : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; vpr_free_all(net_list, Arch, vpr_setup); return ERROR_EXIT_CODE; } catch (const VprError& vpr_error) { vpr_print_error(vpr_error); - const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = + vpr_setup.RouterOpts.flat_routing + ? (const Netlist<>&)g_vpr_ctx.atom().nlist + : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (vpr_error.type() == VPR_ERROR_INTERRUPTED) { vpr_free_all(net_list, Arch, vpr_setup); @@ -162,7 +171,10 @@ static int vpr_standalone(int argc, char** argv) { } catch (const vtr::VtrError& vtr_error) { VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(), vtr_error.what()); - const Netlist<>& net_list = vpr_setup.RouterOpts.flat_routing ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = + vpr_setup.RouterOpts.flat_routing + ? (const Netlist<>&)g_vpr_ctx.atom().nlist + : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; vpr_free_all(net_list, Arch, vpr_setup); return ERROR_EXIT_CODE; From c7203cd6e6d6f7ae88a7b43e141cdee538d81ebe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Apr 2023 11:11:24 +0800 Subject: [PATCH 10/12] [script] revert back the old make all recipe --- Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 49f6a0a73..db960eb5b 100644 --- a/Makefile +++ b/Makefile @@ -79,9 +79,8 @@ list_cmake_targets: prebuild # Show the targets available to be built, which can be specified through ``CMAKE_GOALS`` when compile cd ${BUILD_DIR} && make help && cd - -all: checkout +all: checkout compile # A shortcut command to run checkout and compile in serial - make compile CMAKE_GOALS=${CMAKE_GOALS} format-cpp: # Format all the C/C++ files under this project, excluding submodules From 7d13faffe9e82653cb38560c804f2eca1f0b25ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Apr 2023 11:19:27 +0800 Subject: [PATCH 11/12] [script] now split make checkout and make compile --- .github/workflows/build.yml | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e0cd7bc71..4017fcaf5 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -127,10 +127,15 @@ jobs: - uses: hendrikmuhs/ccache-action@v1 + - name: checkout submodules + shell: bash + run: | + make checkout + - name: Build shell: bash run: | - make all BUILD_TYPE=$BUILD_TYPE + make compile BUILD_TYPE=$BUILD_TYPE # Check the cache size and see if it is over the limit - name: Check ccache size @@ -211,10 +216,15 @@ jobs: - uses: hendrikmuhs/ccache-action@v1 + - name: checkout submodules + shell: bash + run: | + make checkout + - name: Build shell: bash run: | - make all BUILD_TYPE=$BUILD_TYPE CMAKE_FLAGS="${{ matrix.config.cmake_flags }}" + make compile BUILD_TYPE=$BUILD_TYPE CMAKE_FLAGS="${{ matrix.config.cmake_flags }}" ubuntu_support: needs: change_detect @@ -252,10 +262,15 @@ jobs: - uses: hendrikmuhs/ccache-action@v1 + - name: checkout submodules + shell: bash + run: | + make checkout + - name: Build shell: bash run: | - make all BUILD_TYPE=$BUILD_TYPE + make compile BUILD_TYPE=$BUILD_TYPE debug_build: needs: change_detect @@ -300,10 +315,15 @@ jobs: - uses: hendrikmuhs/ccache-action@v1 + - name: checkout submodules + shell: bash + run: | + make checkout + - name: Build shell: bash run: | - make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} + make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} - name: Quick Test shell: bash @@ -351,10 +371,15 @@ jobs: - uses: hendrikmuhs/ccache-action@v1 + - name: checkout submodules + shell: bash + run: | + make checkout + - name: Build shell: bash run: | - make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON" + make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON" - name: Quick Test shell: bash From 9690cea1154417c0c7d905d9cebe968828229aaf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Apr 2023 15:46:42 +0800 Subject: [PATCH 12/12] [core] fix clang syntax --- openfpga/src/mux_lib/mux_library_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/mux_lib/mux_library_builder.cpp b/openfpga/src/mux_lib/mux_library_builder.cpp index add2acf53..9ef612784 100644 --- a/openfpga/src/mux_lib/mux_library_builder.cpp +++ b/openfpga/src/mux_lib/mux_library_builder.cpp @@ -56,7 +56,7 @@ static void build_routing_arch_mux_library( if (CircuitModelId::INVALID() == rr_switch_circuit_model) { VTR_LOG_ERROR( "Unable to find the circuit model for rr_switch '%s'!\n", - rr_graph.rr_switch_inf(driver_switches[0]).name); + rr_graph.rr_switch_inf(driver_switches[0]).name.c_str()); VTR_LOG("Node type: %s\n", rr_graph.node_type_string(node)); VTR_LOG("Node coordinate: %s\n", rr_graph.node_coordinate_to_string(node).c_str());