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start debugging tileable routing using larger array size. Bug spotted in finding chan nodes

This commit is contained in:
tangxifan 2020-03-20 22:12:23 -06:00
parent 682b667a3c
commit 2ff2d65e58
2 changed files with 6 additions and 2 deletions
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4
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -159,9 +159,9 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="false">
<layout tileable="true">
<!--auto_layout aspect_ratio="1.0"-->
<fixed_layout name="2x2" width="3" height="4">
<fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>

4
vpr/src/tileable_rr_graph/rr_gsb.cpp
View File

@ -444,6 +444,10 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph,
/* Reach here it means that this will be a passing wire,
* we should be able to find the node on the opposite side of the GSB!
*/
if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) {
VTR_LOG("GSB[%lu][%lu] track node:\n", get_x(), get_y());
rr_graph.print_node(track_node);
}
VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side));
return true;