From 2ff2d65e583158d333452b04e5d078e1593a5427 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 22:12:23 -0600
Subject: [PATCH] start debugging tileable routing using larger array size. Bug
 spotted in finding chan nodes

---
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml | 4 ++--
 vpr/src/tileable_rr_graph/rr_gsb.cpp                    | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index b1a588eb1..c3598bd2b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,9 +159,9 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="false">
+  <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="3" height="4">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 2d5c08e8c..d3ae2bcc5 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -444,6 +444,10 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph,
   /* Reach here it means that this will be a passing wire, 
    * we should be able to find the node on the opposite side of the GSB!
    */
+  if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) {
+    VTR_LOG("GSB[%lu][%lu] track node:\n", get_x(), get_y());
+    rr_graph.print_node(track_node);
+  }
   VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side));
 
   return true;