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[script] debugging

This commit is contained in:
tangxifan 2022-12-01 12:26:30 -08:00
parent 48a9a97562
commit 2e585024f7
2 changed files with 15 additions and 7 deletions
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15
CMakeLists.txt
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@ -84,6 +84,21 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou
set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing") set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number") set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
# TCL file/lib required to link with SWIG generated wrapper
if (OPENFPGA_WITH_SWIG)
#Find Tcl
include(FindTCL)
message(STATUS "tcl.h path is : ${TCL_INCLUDE_PATH}")
message(STATUS "libtcl.so path is : ${TCL_LIBRARY}")
#Find SWIG
find_package(SWIG 3.0 REQUIRED)
if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
message(WARNING "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
endif()
include(UseSWIG)
endif()
#Compiler flag configuration checks #Compiler flag configuration checks
include(CheckCXXCompilerFlag) include(CheckCXXCompilerFlag)

7
openfpga/CMakeLists.txt
View File

@ -11,13 +11,6 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE}) list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE})
if (OPENFPGA_WITH_SWIG) if (OPENFPGA_WITH_SWIG)
#Find SWIG
find_package(SWIG 3.0 REQUIRED)
if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
message(WARNING "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
endif()
include(UseSWIG)
# SWIG library # SWIG library
SwigLib(NAME openfpga_swig SwigLib(NAME openfpga_swig
NAMESPACE openfpga NAMESPACE openfpga