From 2e585024f710f77adeec60a720ea47eaf72ce75f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Dec 2022 12:26:30 -0800
Subject: [PATCH] [script] debugging

---
 CMakeLists.txt          | 15 +++++++++++++++
 openfpga/CMakeLists.txt |  7 -------
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index a65db3907..31229bc0d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -84,6 +84,21 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou
 set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
 set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
 
+# TCL file/lib required to link with SWIG generated wrapper
+if (OPENFPGA_WITH_SWIG)
+#Find Tcl
+  include(FindTCL)
+  message(STATUS "tcl.h path is : ${TCL_INCLUDE_PATH}")
+  message(STATUS "libtcl.so path is : ${TCL_LIBRARY}") 
+
+#Find SWIG
+  find_package(SWIG 3.0 REQUIRED)
+  if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
+    message(WARNING "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
+  endif()
+  include(UseSWIG)
+endif()
+
 #Compiler flag configuration checks
 include(CheckCXXCompilerFlag)
 
diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt
index 85df53da8..fbb9208fc 100644
--- a/openfpga/CMakeLists.txt
+++ b/openfpga/CMakeLists.txt
@@ -11,13 +11,6 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
 list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE})
 
 if (OPENFPGA_WITH_SWIG)
-#Find SWIG
-  find_package(SWIG 3.0 REQUIRED)
-  if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
-    message(WARNING "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
-  endif()
-  include(UseSWIG)
-
 # SWIG library
   SwigLib(NAME      openfpga_swig
           NAMESPACE openfpga