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[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers

This commit is contained in:
tangxifan 2021-10-01 11:23:40 -07:00
parent cf96d9ff01
commit 2bd2788e77
1 changed files with 24 additions and 2 deletions
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26
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -61,7 +61,18 @@ void print_verilog_top_testbench_ql_memory_bank_port(std::fstream& fp,
} }
} else { } else {
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()); VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
/* TODO */ print_verilog_comment(fp, std::string("---- Bit-Line ports -----"));
for (const ConfigRegionId& region : module_manager.regions(top_module)) {
ModulePortId sr_head_port_id = module_manager.find_module_port(top_module,
generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME), region));
BasicPort sr_head_port = module_manager.module_port(top_module, sr_head_port_id);
fp << generate_verilog_port(VERILOG_PORT_REG, sr_head_port) << ";" << std::endl;
ModulePortId sr_tail_port_id = module_manager.find_module_port(top_module,
generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME), region));
BasicPort sr_tail_port = module_manager.module_port(top_module, sr_tail_port_id);
fp << generate_verilog_port(VERILOG_PORT_WIRE, sr_tail_port) << ";" << std::endl;
}
} }
/* Print the address port for the Word-Line decoder here */ /* Print the address port for the Word-Line decoder here */
@ -82,7 +93,18 @@ void print_verilog_top_testbench_ql_memory_bank_port(std::fstream& fp,
} }
} else { } else {
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type()); VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
/* TODO */ print_verilog_comment(fp, std::string("---- Word-Line ports -----"));
for (const ConfigRegionId& region : module_manager.regions(top_module)) {
ModulePortId sr_head_port_id = module_manager.find_module_port(top_module,
generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME), region));
BasicPort sr_head_port = module_manager.module_port(top_module, sr_head_port_id);
fp << generate_verilog_port(VERILOG_PORT_REG, sr_head_port) << ";" << std::endl;
ModulePortId sr_tail_port_id = module_manager.find_module_port(top_module,
generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME), region));
BasicPort sr_tail_port = module_manager.module_port(top_module, sr_tail_port_id);
fp << generate_verilog_port(VERILOG_PORT_WIRE, sr_tail_port) << ";" << std::endl;
}
} }
/* Print the data-input port: only available when BL has a decoder */ /* Print the data-input port: only available when BL has a decoder */