riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Adding command to generate verilog file out of yosys run

This commit is contained in:
Lalit Sharma 2021-03-05 04:05:19 -08:00
parent 0cbad747a1
commit 2b2acae757
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/misc/qlf_yosys.ys
View File

@ -4,3 +4,4 @@ ${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE} synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}
write_verilog -noattr -nohex ${TOP_MODULE}.v