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[Engine] Bug fix on wrong port type for shift register chains

This commit is contained in:
tangxifan 2021-10-03 12:31:58 -07:00
parent 756b4c7dc8
commit 28904ff526
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fabric/build_top_module_memory_bank.cpp
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@ -1588,7 +1588,7 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
BasicPort blsr_head_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads); BasicPort blsr_head_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads);
module_manager.add_port(module_id, blsr_head_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(module_id, blsr_head_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort blsr_tail_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads); BasicPort blsr_tail_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads);
module_manager.add_port(module_id, blsr_tail_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(module_id, blsr_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
} }
break; break;
} }
@ -1637,7 +1637,7 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
BasicPort wlsr_head_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads); BasicPort wlsr_head_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads);
module_manager.add_port(module_id, wlsr_head_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(module_id, wlsr_head_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort wlsr_tail_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads); BasicPort wlsr_tail_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads);
module_manager.add_port(module_id, wlsr_tail_port, ModuleManager::MODULE_INPUT_PORT); module_manager.add_port(module_id, wlsr_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
} }
break; break;
} }