From 28904ff526e2b73fae3d74fa3b745fd97831d451 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Oct 2021 12:31:58 -0700 Subject: [PATCH] [Engine] Bug fix on wrong port type for shift register chains --- openfpga/src/fabric/build_top_module_memory_bank.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp index 031e0a8aa..dd3dceafb 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.cpp +++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp @@ -1588,7 +1588,7 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager, BasicPort blsr_head_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads); module_manager.add_port(module_id, blsr_head_port, ModuleManager::MODULE_INPUT_PORT); BasicPort blsr_tail_port(generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads); - module_manager.add_port(module_id, blsr_tail_port, ModuleManager::MODULE_INPUT_PORT); + module_manager.add_port(module_id, blsr_tail_port, ModuleManager::MODULE_OUTPUT_PORT); } break; } @@ -1637,7 +1637,7 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager, BasicPort wlsr_head_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region), num_heads); module_manager.add_port(module_id, wlsr_head_port, ModuleManager::MODULE_INPUT_PORT); BasicPort wlsr_tail_port(generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region), num_heads); - module_manager.add_port(module_id, wlsr_tail_port, ModuleManager::MODULE_INPUT_PORT); + module_manager.add_port(module_id, wlsr_tail_port, ModuleManager::MODULE_OUTPUT_PORT); } break; }