riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Add the new test case to regression tests

This commit is contained in:
tangxifan 2022-02-01 13:45:46 -08:00
parent 532af96243
commit 27ac2fafe5
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
View File

@ -146,3 +146,4 @@ run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug -
echo -e "Testing the netlist generation by forcing the use of relative paths";
run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path --debug --show_thread_logs