diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
index 7d781e7be..aea6a3459 100755
--- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
@@ -146,3 +146,4 @@ run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug -
 
 echo -e "Testing the netlist generation by forcing the use of relative paths";
 run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs
+run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path --debug --show_thread_logs