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use index range instead of vector for block bitstream

This commit is contained in:
tangxifan 2020-07-03 11:42:38 -06:00
parent 6ea857ae6c
commit 2783fda344
5 changed files with 39 additions and 56 deletions
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39
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
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@ -77,7 +77,16 @@ std::vector<ConfigBitId> BitstreamManager::block_bits(const ConfigBlockId& block
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return block_bit_ids_[block_id];
size_t lsb = block_bit_id_lsbs_[block_id];
size_t msb = block_bit_id_msbs_[block_id];
std::vector<ConfigBitId> bits(msb - lsb + 1, ConfigBitId::INVALID());
for (size_t i = lsb; i < msb + 1; ++i) {
bits[i - lsb] = ConfigBitId(i);
}
return bits;
}
/* Find the child block in a bitstream manager with a given name */
@ -142,7 +151,8 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
void BitstreamManager::reserve_blocks(const size_t& num_blocks) {
block_names_.reserve(num_blocks);
block_bit_ids_.reserve(num_blocks);
block_bit_id_lsbs_.reserve(num_blocks);
block_bit_id_msbs_.reserve(num_blocks);
block_path_ids_.reserve(num_blocks);
block_input_net_ids_.reserve(num_blocks);
block_output_net_ids_.reserve(num_blocks);
@ -159,7 +169,8 @@ ConfigBlockId BitstreamManager::create_block() {
/* Add a new bit, and allocate associated data structures */
num_blocks_++;
block_names_.emplace_back();
block_bit_ids_.emplace_back();
block_bit_id_lsbs_.emplace_back(0);
block_bit_id_msbs_.emplace_back(-1);
block_path_ids_.push_back(-2);
block_input_net_ids_.emplace_back();
block_output_net_ids_.emplace_back();
@ -201,21 +212,19 @@ void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const
parent_block_ids_[child_block] = parent_block;
}
void BitstreamManager::reserve_block_bits(const ConfigBlockId& block,
const size_t& num_bits) {
void BitstreamManager::add_block_bits(const ConfigBlockId& block,
const std::vector<bool>& block_bitstream) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_bit_ids_[block].reserve(num_bits);
}
void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
VTR_ASSERT(true == valid_bit_id(bit));
/* Add the bit to the block */
block_bit_ids_[block].push_back(bit);
/* Add the bit to the block, record anchors in bit indexing for block-level searching */
size_t lsb = num_bits_;
size_t msb = num_bits_ + block_bitstream.size() - 1;
for (const bool& bit : block_bitstream) {
add_bit(bit);
}
block_bit_id_lsbs_[block] = lsb;
block_bit_id_msbs_[block] = msb;
}
void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const int& path_id) {

12
libopenfpga/libfpgabitstream/src/bitstream_manager.h
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@ -166,12 +166,9 @@ class BitstreamManager {
/* Set a block as a child block of another */
void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
/* Reserve a number of configuration bits for a block */
void reserve_block_bits(const ConfigBlockId& block,
const size_t& num_bits);
/* Add a configuration bit to a block */
void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit);
/* Add a bitstream to a block */
void add_block_bits(const ConfigBlockId& block,
const std::vector<bool>& block_bitstream);
/* Add a path id to a block */
void add_path_id_to_block(const ConfigBlockId& block, const int& path_id);
@ -199,7 +196,8 @@ class BitstreamManager {
/* Unique id of a block of bits in the Bitstream */
size_t num_blocks_;
std::unordered_set<ConfigBlockId> invalid_block_ids_;
vtr::vector<ConfigBlockId, std::vector<ConfigBitId>> block_bit_ids_;
vtr::vector<ConfigBlockId, size_t> block_bit_id_lsbs_;
vtr::vector<ConfigBlockId, size_t> block_bit_id_msbs_;
/* Back-annotation for the bits */
/* Parent block of a bit in the Bitstream

9
libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp
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@ -101,16 +101,17 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block,
}
/* Find the child paths/nets */
std::vector<bool> block_bits;
for (pugi::xml_node xml_bit : xml_bitstream.children()) {
/* We only care child bitstream blocks here */
if (xml_bit.name() != std::string("bit")) {
bad_tag(xml_bit, loc_data, xml_bitstream, {"bit"});
}
const int& bit_value = get_attribute(xml_bit, "value", loc_data).as_int();
ConfigBitId bit = bitstream_manager.add_bit(1 == bit_value);
/* Link the bit to parent block */
bitstream_manager.add_bit_to_block(curr_block, bit);
}
block_bits.push_back(1 == bit_value);
}
/* Link the bit to parent block */
bitstream_manager.add_block_bits(curr_block, block_bits);
}
/* Go recursively: find all the child blocks and parse */

21
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -106,12 +106,7 @@ void build_primitive_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_child_block(parent_configurable_block, mem_block);
/* Add the bitstream to the bitstream manager */
bitstream_manager.reserve_block_bits(mem_block, mode_select_bitstream.size());
for (const bool& bit : mode_select_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
bitstream_manager.add_bit_to_block(mem_block, config_bit);
}
bitstream_manager.add_block_bits(mem_block, mode_select_bitstream);
}
/********************************************************************
@ -215,12 +210,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
}
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
@ -469,12 +459,7 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_child_block(parent_configurable_block, mem_block);
/* Add the bitstream to the bitstream manager */
bitstream_manager.reserve_block_bits(mem_block, lut_bitstream.size());
for (const bool& bit : lut_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
bitstream_manager.add_bit_to_block(mem_block, config_bit);
}
bitstream_manager.add_block_bits(mem_block, lut_bitstream);
}
/********************************************************************

14
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -98,12 +98,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
}
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
@ -292,12 +287,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
}
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());