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[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition

This commit is contained in:
tangxifan 2021-10-06 13:38:51 -07:00
parent dc5aedc393
commit 27153bbc89
1 changed files with 2 additions and 1 deletions
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3
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -297,7 +297,7 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
float& sr_clock_period) {
for (const SimulationClockId& sim_clk : sim_settings.programming_shift_register_clocks()) {
/* Bypass all the clocks which does not match */
if (sim_settings.clock_port(sim_clk) == sr_clock_port && sim_settings.constrained_clock(sim_clk)) {
if (sim_settings.clock_name(sim_clk) == sr_clock_port.get_name() && sim_settings.constrained_clock(sim_clk)) {
if (sr_clock_period > 0.5 * (1 / sim_settings.clock_frequency(sim_clk)) / timescale) {
VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s)! Shift register chain cannot load data completely!\n",
1. / (2. * sr_clock_period * timescale) / 1e6,
@ -310,6 +310,7 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
time_unit_to_string(1e6, "Hz").c_str(),
sr_clock_port.get_name().c_str());
}
break;
}
}
return CMD_EXEC_SUCCESS;