From 27153bbc899cba16d92ecdd5e735e828b569b13c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 Oct 2021 13:38:51 -0700
Subject: [PATCH] [FPGA-Verilog] Bug fix in matching shift register clocks
 between verilog ports and simulation setting definition

---
 .../src/fpga_verilog/verilog_top_testbench_memory_bank.cpp     | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
index 12fc89139..9f12362b5 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
@@ -297,7 +297,7 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
                                                                         float& sr_clock_period) {
   for (const SimulationClockId& sim_clk : sim_settings.programming_shift_register_clocks()) {
     /* Bypass all the clocks which does not match */
-    if (sim_settings.clock_port(sim_clk) == sr_clock_port && sim_settings.constrained_clock(sim_clk)) {
+    if (sim_settings.clock_name(sim_clk) == sr_clock_port.get_name() && sim_settings.constrained_clock(sim_clk)) {
       if (sr_clock_period > 0.5 * (1 / sim_settings.clock_frequency(sim_clk)) / timescale) {
         VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s)! Shift register chain cannot load data completely!\n",
                       1. / (2. * sr_clock_period * timescale) / 1e6,
@@ -310,6 +310,7 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
                 time_unit_to_string(1e6, "Hz").c_str(),
                 sr_clock_port.get_name().c_str());
       }
+      break;
     }
   }
   return CMD_EXEC_SUCCESS;