[test] update pin constraints

This commit is contained in:
tangxifan 2023-01-13 21:12:18 -08:00
parent 1b06916e57
commit 26f71656de
4 changed files with 7 additions and 6 deletions

View File

@ -0,0 +1,4 @@
<pin_constraints>
<set_io pin="op_clk[0]" net="clk_i"/>
</pin_constraints>

View File

@ -1,4 +0,0 @@
<pin_constraints>
<!-- Intended to be dummy -->
</pin_constraints>

View File

@ -1,4 +1,5 @@
<repack_design_constraints>
<!-- Intended to be dummy -->
<pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
<!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
</repack_design_constraints>

View File

@ -36,7 +36,7 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = clk_divider
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=