[test] update pin constraints
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1b06916e57
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@ -0,0 +1,4 @@
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<pin_constraints>
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<set_io pin="op_clk[0]" net="clk_i"/>
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</pin_constraints>
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<pin_constraints>
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<!-- Intended to be dummy -->
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</pin_constraints>
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@ -1,4 +1,5 @@
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<repack_design_constraints>
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<!-- Intended to be dummy -->
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<pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
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<!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
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</repack_design_constraints>
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@ -36,7 +36,7 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
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bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
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bench0_top = clk_divider
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bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
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bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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