From 26f71656de775559eb00e28b78a918936fc52162 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 21:12:18 -0800
Subject: [PATCH] [test] update pin constraints

---
 .../k4_series/k4n4_clk_gen/config/pin_constraints.xml         | 4 ++++
 .../k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml   | 4 ----
 .../k4n4_clk_gen/config/repack_design_constraints.xml         | 3 ++-
 .../tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf | 2 +-
 4 files changed, 7 insertions(+), 6 deletions(-)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
 delete mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
new file mode 100644
index 000000000..0b33739fe
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints.xml
@@ -0,0 +1,4 @@
+<pin_constraints>
+  <set_io pin="op_clk[0]" net="clk_i"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
deleted file mode 100644
index 20a21d2cf..000000000
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
+++ /dev/null
@@ -1,4 +0,0 @@
-<pin_constraints>
-  <!-- Intended to be dummy -->
-</pin_constraints>
-
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
index 06a125111..76ca10a78 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
@@ -1,4 +1,5 @@
 <repack_design_constraints>
-  <!-- Intended to be dummy -->
+  <pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
+  <!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
 </repack_design_constraints>
 
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index d78597e11..d889031ed 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -36,7 +36,7 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench0_top = clk_divider
-bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=