riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

add priority info to fpga_bitstream_commands.rst

This commit is contained in:
Jingrong Lin 2023-12-04 14:37:46 +08:00 committed by GitHub
parent 9ffdcbff05
commit 26b2eb0970
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
View File

@ -29,7 +29,8 @@ Repack's functionality are in the following aspects:
Specify the mapping results of global nets should be ignored on which pins of a ``pb_type``. For example, ``--ignore_global_nets_on_pins clb.I[0:11]``. Once specified, the mapping results on the pins for all the global nets, such as clock, reset *etc.*, are ignored. Routing traces will be appeneded to other pins where the same global nets are mapped to.
.. note:: This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes!
.. note:: - This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes!
- For repack options, the constraints specified by ``--ignore_global_nets_on_pins`` have higher priority than those set by ``ignore_net``. When the constraints from ``--ignore_global_nets_on_pins`` are satisfied, those from ``ignore_net`` will not be checked. For more information on ``ignore_net``, see `Repack Design Constraints (.xml) <../../file_formats/repack_design_constraints.rst>`_.
.. warning:: Users must specify the size/width of the pin. Currently, OpenFPGA cannot infer the pin size from the architecture!!!