Update repack_design_constraints.rst
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@ -13,10 +13,12 @@ An example of design constraints is shown as follows.
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.. code-block:: xml
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="reset[0]" net="rst_n"/>
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<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
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<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
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<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
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<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
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<ignore_net name="rst_n" pin="clb.I[0:11]"/>
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</repack_design_constraints>
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.. option:: pb_type="<string>"
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@ -33,18 +35,7 @@ An example of design constraints is shown as follows.
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.. warning:: Design constraints is a feature for power-users. It may cause repack to fail. It is users's responsibility to ensure proper design constraints
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**Addtional command:** To bypass global nets on specified pins, we add additional command: ignore_net
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An example of setting ignore nets is shown as follows.
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.. code-block:: xml
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
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...
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<ignore_net name="rst_n" pin="clb.I[0:11]"/>
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<ignore_net name="rst_n" pin="dsp.I[0:11]"/>
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</repack_design_constraints>
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**Addtional command:** To ignore the global nets on specific pins, use the syntax ``ignore_net``. Note that the qualified pins are inputs, outputs, and clocks of pb_type. The option is useful for preventing global nets from being assigned to unwanted pins on pb_type.
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.. option:: name="<string>"
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