riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[lib] first round of data structure on clock arch

This commit is contained in:
tangxifan 2023-02-22 12:18:44 -08:00
parent 9eb2374bc6
commit 25e43b47da
2 changed files with 41 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

132
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -14,128 +14,72 @@ namespace openfpga { // Begin namespace openfpga
/************************************************************************
* Constructors
***********************************************************************/
ClockNetwork::ClockNetwork() { return; }
ClockNetwork::ClockNetwork() {
is_dirty_ = true;
}
/************************************************************************
* Public Accessors : aggregates
***********************************************************************/
ClockNetwork::bus_group_range ClockNetwork::buses() const {
return vtr::make_range(bus_ids_.begin(), bus_ids_.end());
ClockNetwork::clock_tree_range ClockNetwork::trees() const {
return vtr::make_range(tree_ids_.begin(), tree_ids_.end());
}
/************************************************************************
* Public Accessors : Basic data query
***********************************************************************/
openfpga::BasicPort ClockNetwork::bus_port(const ClockNetworkId& bus_id) const {
VTR_ASSERT(valid_bus_id(bus_id));
return bus_ports_[bus_id];
}
bool ClockNetwork::is_big_endian(const ClockNetworkId& bus_id) const {
VTR_ASSERT(valid_bus_id(bus_id));
return bus_big_endians_[bus_id];
}
std::vector<BusPinId> ClockNetwork::bus_pins(const ClockNetworkId& bus_id) const {
VTR_ASSERT(valid_bus_id(bus_id));
return bus_pin_ids_[bus_id];
}
int ClockNetwork::pin_index(const BusPinId& pin_id) const {
VTR_ASSERT(valid_pin_id(pin_id));
return pin_indices_[pin_id];
}
std::string ClockNetwork::pin_name(const BusPinId& pin_id) const {
VTR_ASSERT(valid_pin_id(pin_id));
return pin_names_[pin_id];
}
ClockNetworkId ClockNetwork::find_pin_bus(const std::string& pin_name) const {
std::map<std::string, BusPinId>::const_iterator result =
pin_name2id_map_.find(pin_name);
if (result == pin_name2id_map_.end()) {
/* Not found, return an invalid id */
return ClockNetworkId::INVALID();
}
/* Found, we should get the parent bus */
BusPinId pin_id = result->second;
return pin_parent_bus_ids_[pin_id];
}
ClockNetworkId ClockNetwork::find_bus(const std::string& bus_name) const {
std::map<std::string, ClockNetworkId>::const_iterator result =
bus_name2id_map_.find(bus_name);
if (result == bus_name2id_map_.end()) {
/* Not found, return an invalid id */
return ClockNetworkId::INVALID();
}
/* Found, we should get the parent bus */
return result->second;
}
BusPinId ClockNetwork::find_pin(const std::string& pin_name) const {
std::map<std::string, BusPinId>::const_iterator result =
pin_name2id_map_.find(pin_name);
if (result == pin_name2id_map_.end()) {
/* Not found, return an invalid id */
return BusPinId::INVALID();
}
/* Found, we should get the parent bus */
return result->second;
}
bool ClockNetwork::empty() const { return 0 == bus_ids_.size(); }
bool ClockNetwork::empty() const { return 0 == tree_ids_.size(); }
/************************************************************************
* Public Mutators
***********************************************************************/
void ClockNetwork::reserve_buses(const size_t& num_buses) {
bus_ids_.reserve(num_buses);
bus_ports_.reserve(num_buses);
bus_big_endians_.reserve(num_buses);
bus_pin_ids_.reserve(num_buses);
void ClockNetwork::reserve_spines(const size_t& num_spines) {
spine_ids_.reserve(num_spines);
spine_names_.reserve(num_spines);
spine_levels_.reserve(num_spines);
spine_start_points_.reserve(num_spines);
spine_end_points_.reserve(num_spines);
spine_switch_points_.reserve(num_spines);
spine_switch_coords_.reserve(num_spines);
spine_parent_.reserve(num_spines);
spine_parent_tree_.reserve(num_spines);
}
void ClockNetwork::reserve_pins(const size_t& num_pins) {
pin_ids_.reserve(num_pins);
pin_indices_.reserve(num_pins);
pin_names_.reserve(num_pins);
pin_parent_bus_ids_.reserve(num_pins);
void ClockNetwork::reserve_trees(const size_t& num_trees) {
tree_ids_.reserve(num_trees);
tree_names_.reserve(num_trees);
tree_widths_.reserve(num_trees);
tree_top_spines_.reserve(num_trees);
}
ClockNetworkId ClockNetwork::create_bus(const openfpga::BasicPort& bus_port) {
ClockTreeId ClockNetwork::create_tree(const std::string& name, const size_t& width = 1) {
/* Create a new id */
ClockNetworkId bus_id = ClockNetworkId(bus_ids_.size());
ClockTreeId tree_id = ClockTreeId(tree_ids_.size());
bus_ids_.push_back(bus_id);
bus_ports_.push_back(bus_port);
bus_big_endians_.push_back(true);
bus_pin_ids_.emplace_back();
tree_ids_.push_back(tree_id);
tree_names_.push_back(name);
tree_widths_.push_back(width);
tree_top_spines_.emplace_back();
/* Register to fast look-up */
auto result = bus_name2id_map_.find(bus_port.get_name());
if (result == bus_name2id_map_.end()) {
bus_name2id_map_[bus_port.get_name()] = bus_id;
auto result = tree_name2id_map_.find(name);
if (result == tree_name2id_map_.end()) {
tree_name2id_map_[name] = tree_id;
} else {
VTR_LOG_ERROR("Duplicated bus name '%s' in bus group",
bus_port.get_name().c_str());
VTR_LOG_ERROR("Duplicated clock tree name '%s' in clock network\n",
name.c_str());
exit(1);
}
return bus_id;
}
void ClockNetwork::set_bus_big_endian(const ClockNetworkId& bus_id,
const bool& big_endian) {
VTR_ASSERT(valid_bus_id(bus_id));
bus_big_endians_[bus_id] = big_endian;
return tree_id;
}
ClockSpineId ClockNetwork::create_spine(const std::string& name) {
/* Check if the name is already used or not */
auto result = spine_name2ids_.find(name);
if (result != spine_name2ids_.end()) {
auto result = spine_name2id_map_.find(name);
if (result != spine_name2id_map_.end()) {
VTR_LOG_WARN("Unable to create a spine with duplicated name '%s' in clock network\nPlease use the existing spine or rename\n",
name.c_str());
return ClockSpineId::INVALID();
}
@ -154,7 +98,7 @@ ClockSpineId ClockNetwork::create_spine(const std::string& name) {
spine_parent_tree_.emplace_back();
/* Register to the lookup */
spine_name2ids_[name] = spine_id;
spine_name2id_map_[name] = spine_id;
return spine_id;
}

7
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -49,9 +49,6 @@ class ClockNetwork {
clock_tree_range trees() const;
public: /* Public Accessors: Basic data query */
/* Find a spine by name, return a valid id if found, otherwise return an invalid id */
ClockSpineId spine(const std::string& name) const;
/* Check if there are clock tree */
bool empty() const;
@ -85,6 +82,7 @@ class ClockNetwork {
/* Basic information of each tree */
vtr::vector<ClockTreeId, ClockTreeId> tree_ids_;
vtr::vector<ClockTreeId, std::string> tree_names_;
vtr::vector<ClockTreeId, size_t> tree_widths_;
vtr::vector<ClockTreeId, std::vector<ClockSpineId>> tree_top_spines_;
/* Basic information of each spine */
@ -99,7 +97,8 @@ class ClockNetwork {
vtr::vector<ClockSpineId, ClockTreeId> spine_parent_tree_;
/* Fast lookup */
std::map<std::string, ClockSpineId> spine_name2ids_;
std::map<std::string, ClockTreeId> tree_name2id_map_;
std::map<std::string, ClockSpineId> spine_name2id_map_;
/* Flags */
bool is_dirty_;