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use more robust net builder in inter tile connections

This commit is contained in:
tangxifan 2020-06-30 10:49:17 -06:00
parent 025d4a3599
commit 23bcad0678
1 changed files with 4 additions and 4 deletions
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8
openfpga/src/fabric/build_top_module_directs.cpp
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@ -125,10 +125,10 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0);
module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0);
/* Create the 2nd module net */
ModuleNetId net_direct_sink = module_manager.create_module_net(top_module);
/* Connect the wire between direct_instance output and sink_pin of clb */
module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0);
/* Create the 2nd module net
* Connect the wire between direct_instance output and sink_pin of clb
*/
ModuleNetId net_direct_sink = create_module_source_pin_net(module_manager, top_module, direct_module, direct_instance_id, direct_output_port_id, 0);
module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0);
}