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minor tweak on the scan-chain support in VPR8 as well as architecture file 

Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
This commit is contained in:
tangxifan 2020-04-07 17:03:44 -06:00
parent 50bb04d496
commit 2342d7cdc6
2 changed files with 7 additions and 3 deletions
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3
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
View File

@ -720,13 +720,10 @@
<direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin"> <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/> <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
<pack_pattern name="chain" in_port="clb.scin" out_port="fle[0:0].scin"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout"> <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
<pack_pattern name="chain" in_port="fle[9:9].scout" out_port="clb.scout"/>
</direct> </direct>
<direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin"> <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
<pack_pattern name="chain" in_port="fle[8:0].scout" out_port="fle[9:1].scin"/>
</direct> </direct>
</interconnect> </interconnect>
</pb_type> </pb_type>

7
vpr/src/pack/prepack.cpp
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@ -1557,6 +1557,13 @@ static t_pb_graph_pin* get_connected_primitive_pin(const t_pb_graph_pin* cluster
* will be only one pin connected to the very first adder in the cluster. * will be only one pin connected to the very first adder in the cluster.
*/ */
static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector<t_pb_graph_pin*>& connected_primitive_pins) { static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector<t_pb_graph_pin*>& connected_primitive_pins) {
/* Xifan Tang: Skip pins belong to unpackable modes */
if ( (nullptr != cluster_input_pin->parent_node->pb_type->parent_mode)
&& (false == cluster_input_pin->parent_node->pb_type->parent_mode->packable) ) {
return;
}
for (int iedge = 0; iedge < cluster_input_pin->num_output_edges; iedge++) { for (int iedge = 0; iedge < cluster_input_pin->num_output_edges; iedge++) {
const auto& output_edge = cluster_input_pin->output_edges[iedge]; const auto& output_edge = cluster_input_pin->output_edges[iedge];
for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) { for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) {