From 2342d7cdc6c54f9cdeccc59315640e8392f041fa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 17:03:44 -0600
Subject: [PATCH] minor tweak on the scan-chain support in VPR8 as well as
 architecture file Do NOT use pack patterns for the scan-chain. It will cause
 searching root chain in VPR8 to fail Actually, we do not use scan-chain in
 mapping designs. Disable the pack pattern has no impact

---
 ...k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml | 3 ---
 vpr/src/pack/prepack.cpp                                   | 7 +++++++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 3b79b1df0..0bce05d74 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -720,13 +720,10 @@
         <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
           <!-- Put all inter-block carry chain delay on this one edge -->
           <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
-          <pack_pattern name="chain" in_port="clb.scin" out_port="fle[0:0].scin"/>
         </direct>
         <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
-          <pack_pattern name="chain" in_port="fle[9:9].scout" out_port="clb.scout"/>
         </direct>
         <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
-          <pack_pattern name="chain" in_port="fle[8:0].scout" out_port="fle[9:1].scin"/>
         </direct>
       </interconnect>
     </pb_type>
diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp
index cf9ccdd6d..dd9d1da3f 100644
--- a/vpr/src/pack/prepack.cpp
+++ b/vpr/src/pack/prepack.cpp
@@ -1557,6 +1557,13 @@ static t_pb_graph_pin* get_connected_primitive_pin(const t_pb_graph_pin* cluster
  *  will be only one pin connected to the very first adder in the cluster.
  */
 static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector<t_pb_graph_pin*>& connected_primitive_pins) {
+
+    /* Xifan Tang: Skip pins belong to unpackable modes */
+    if ( (nullptr != cluster_input_pin->parent_node->pb_type->parent_mode)
+       && (false == cluster_input_pin->parent_node->pb_type->parent_mode->packable) ) {
+        return;
+    }
+
     for (int iedge = 0; iedge < cluster_input_pin->num_output_edges; iedge++) {
         const auto& output_edge = cluster_input_pin->output_edges[iedge];
         for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) {