[core] code format

openfpga/src/annotation/openfpga_annotate_routing.cpp

@@ -73,14 +73,17 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
       }
       VTR_ASSERT(node_pin_num < phy_tile->num_pins);
       t_rr_type rr_pin_type = IPIN;
-      if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == RECEIVER) {
+      if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type ==
+          RECEIVER) {
         rr_pin_type = IPIN;
-      } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == DRIVER) {
+      } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type ==
+                 DRIVER) {
         rr_pin_type = OPIN;
       } else {
-        VTR_LOG_ERROR("When annotating global net '%s', invalid rr node pin type for '%s' pin '%d'\n",
+        VTR_LOG_ERROR(
-                 cluster_nlist.net_name(net_id).c_str(), phy_tile->name,
+          "When annotating global net '%s', invalid rr node pin type for '%s' "
-                 node_pin_num);
+          "pin '%d'\n",
+          cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num);
         exit(1);
       }
       std::vector<RRNodeId> curr_rr_nodes =

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -65,8 +65,10 @@ static void print_verilog_preconfig_top_module_ports(
     /* The block may be renamed as it contains special characters which violate
      * Verilog syntax */
     if (true == netlist_annotation.is_block_renamed(atom_blk)) {
-      VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", block_name.c_str(),
+      VTR_LOG(
-              netlist_annotation.block_name(atom_blk).c_str());
+        "Replace pin name '%s' with '%s' as it is renamed to comply verilog "
+        "syntax\n",
+        block_name.c_str(), netlist_annotation.block_name(atom_blk).c_str());
       block_name = netlist_annotation.block_name(atom_blk);
     }
     /* For output block, remove the prefix which is added by VPR */
@@ -447,8 +449,8 @@ int print_verilog_preconfig_top_module(
   /* Connect FPGA top module global ports to constant or benchmark global
    * signals! */
   status = print_verilog_preconfig_top_module_connect_global_ports(
-    fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
+    fp, module_manager, core_module, pin_constraints, atom_ctx,
-    benchmark_clock_port_names,
+    netlist_annotation, global_ports, benchmark_clock_port_names,
     std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;

openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp

@@ -57,8 +57,7 @@ void print_verilog_preconfig_top_module_internal_wires(
 int print_verilog_preconfig_top_module_connect_global_ports(
   std::fstream &fp, const ModuleManager &module_manager,
   const ModuleId &top_module, const PinConstraints &pin_constraints,
-  const AtomContext& atom_ctx,
+  const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation,
-  const VprNetlistAnnotation &netlist_annotation,
   const FabricGlobalPortInfo &fabric_global_ports,
   const std::vector<std::string> &benchmark_clock_port_names,
   const std::string &port_postfix) {
@@ -123,17 +122,25 @@ int print_verilog_preconfig_top_module_connect_global_ports(
           }
           clock_name_to_connect = benchmark_clock_port_names[pin_id];
         }
-        /* The clock name must be a valid primary input. Otherwise, it could be a signal generated by internal logics, e.g., clb */
+        /* The clock name must be a valid primary input. Otherwise, it could be
+         * a signal generated by internal logics, e.g., clb */
         AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect);
         if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) {
-          VTR_LOG("Global net '%s' is not a primary input of the netlist (which could a signal generated by internal logic). Will not wire it to any FPGA primary input pin\n", clock_name_to_connect.c_str());
+          VTR_LOG(
+            "Global net '%s' is not a primary input of the netlist (which "
+            "could a signal generated by internal logic). Will not wire it to "
+            "any FPGA primary input pin\n",
+            clock_name_to_connect.c_str());
           continue;
         }
-        /* The block may be renamed as it contains special characters which violate
+        /* The block may be renamed as it contains special characters which
-         * Verilog syntax */
+         * violate Verilog syntax */
         if (true == netlist_annotation.is_block_renamed(atom_blk)) {
-          VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", clock_name_to_connect.c_str(),
+          VTR_LOG(
-                  netlist_annotation.block_name(atom_blk).c_str());
+            "Replace pin name '%s' with '%s' as it is renamed to comply "
+            "verilog syntax\n",
+            clock_name_to_connect.c_str(),
+            netlist_annotation.block_name(atom_blk).c_str());
           clock_name_to_connect = netlist_annotation.block_name(atom_blk);
         }
         BasicPort benchmark_clock_pin(clock_name_to_connect, 1);

openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h

@@ -35,8 +35,7 @@ void print_verilog_preconfig_top_module_internal_wires(
 int print_verilog_preconfig_top_module_connect_global_ports(
   std::fstream &fp, const ModuleManager &module_manager,
   const ModuleId &top_module, const PinConstraints &pin_constraints,
-  const AtomContext& atom_ctx,
+  const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation,
-  const VprNetlistAnnotation &netlist_annotation,
   const FabricGlobalPortInfo &fabric_global_ports,
   const std::vector<std::string> &benchmark_clock_port_names,
   const std::string &port_postfix);

openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp

@@ -90,8 +90,9 @@ int print_verilog_testbench_io_connection(
   /* Connect FPGA top module global ports to constant or benchmark global
    * signals! */
   status = print_verilog_preconfig_top_module_connect_global_ports(
-    fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
+    fp, module_manager, core_module, pin_constraints, atom_ctx,
-    benchmark_clock_port_names, std::string());
+    netlist_annotation, global_ports, benchmark_clock_port_names,
+    std::string());
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
   }