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[core] fixed a bug where clock network size cannot impact global port on top module

This commit is contained in:
tangxifan 2024-06-29 17:35:47 -07:00
parent 5dd0549aed
commit 1fd974d544
3 changed files with 23 additions and 9 deletions
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6
libs/libarchopenfpga/src/tile_annotation.cpp
View File

@ -96,6 +96,12 @@ size_t TileAnnotation::global_port_default_value(
return global_port_default_values_[global_port_id]; return global_port_default_values_[global_port_id];
} }
bool TileAnnotation::global_port_thru_dedicated_network(
const TileGlobalPortId& global_port_id) const {
return !global_port_clock_arch_tree_name(global_port_id).empty();
}
std::string TileAnnotation::global_port_clock_arch_tree_name( std::string TileAnnotation::global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id) const { const TileGlobalPortId& global_port_id) const {
VTR_ASSERT(valid_global_port_id(global_port_id)); VTR_ASSERT(valid_global_port_id(global_port_id));

2
libs/libarchopenfpga/src/tile_annotation.h
View File

@ -54,6 +54,8 @@ class TileAnnotation {
bool global_port_is_clock(const TileGlobalPortId& global_port_id) const; bool global_port_is_clock(const TileGlobalPortId& global_port_id) const;
bool global_port_is_set(const TileGlobalPortId& global_port_id) const; bool global_port_is_set(const TileGlobalPortId& global_port_id) const;
bool global_port_is_reset(const TileGlobalPortId& global_port_id) const; bool global_port_is_reset(const TileGlobalPortId& global_port_id) const;
bool global_port_thru_dedicated_network(
const TileGlobalPortId& global_port_id) const;
std::string global_port_clock_arch_tree_name( std::string global_port_clock_arch_tree_name(
const TileGlobalPortId& global_port_id) const; const TileGlobalPortId& global_port_id) const;
size_t global_port_default_value( size_t global_port_default_value(

24
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -1242,11 +1242,11 @@ static int build_top_module_global_net_from_clock_arch_tree(
if (clk_ntwk.tree_width(clk_tree) != if (clk_ntwk.tree_width(clk_tree) !=
module_manager.module_port(top_module, top_module_port).get_width()) { module_manager.module_port(top_module, top_module_port).get_width()) {
VTR_LOG( VTR_LOG(
"Clock tree '%s' does not have the same width '%lu' as the port '%'s of " "Clock tree '%s' does not have the same width '%lu' as the port '%s' of "
"FPGA top module", "FPGA top module",
clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree),
module_manager.module_port(top_module, top_module_port) module_manager.module_port(top_module, top_module_port)
.get_name() .to_verilog_string()
.c_str()); .c_str());
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }
@ -1323,12 +1323,19 @@ int add_top_module_global_ports_from_grid_modules(
BasicPort global_port_to_add; BasicPort global_port_to_add;
global_port_to_add.set_name( global_port_to_add.set_name(
tile_annotation.global_port_name(tile_global_port)); tile_annotation.global_port_name(tile_global_port));
size_t max_port_size = 0; /* Dedicated network has their own sizes of port */
for (const BasicPort& tile_port : if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
tile_annotation.global_port_tile_ports(tile_global_port)) { std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port);
max_port_size = std::max(tile_port.get_width(), max_port_size); ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name);
global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree));
} else {
size_t max_port_size = 0;
for (const BasicPort& tile_port :
tile_annotation.global_port_tile_ports(tile_global_port)) {
max_port_size = std::max(tile_port.get_width(), max_port_size);
}
global_port_to_add.set_width(max_port_size);
} }
global_port_to_add.set_width(max_port_size);
global_ports_to_add.push_back(global_port_to_add); global_ports_to_add.push_back(global_port_to_add);
} }
} }
@ -1352,8 +1359,7 @@ int add_top_module_global_ports_from_grid_modules(
* - If the net will be directly wired to tiles, the net will drive an input * - If the net will be directly wired to tiles, the net will drive an input
* of a tile * of a tile
*/ */
if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port) if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
.empty()) {
status = build_top_module_global_net_from_clock_arch_tree( status = build_top_module_global_net_from_clock_arch_tree(
module_manager, top_module, top_module_port, rr_graph, device_rr_gsb, module_manager, top_module, top_module_port, rr_graph, device_rr_gsb,
cb_instance_ids, clk_ntwk, cb_instance_ids, clk_ntwk,