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[doc] updated vpr arch naming rules

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tangxifan 2023-01-13 19:52:58 -08:00
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openfpga_flow/vpr_arch/README.md
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@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s
- registerable\_io: If I/Os are registerable (can be either combinational or sequential) - registerable\_io: If I/Os are registerable (can be either combinational or sequential)
- CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax
- rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture
- localClkGen: The clock signal of CLB can be generated by internal programmable resources
- <feature\_size>: The technology node which the delay numbers are extracted from. - <feature\_size>: The technology node which the delay numbers are extracted from.
- TileOrgz<Type>: How tile is organized. - TileOrgz<Type>: How tile is organized.
* Top-left (Tl): the pins of a tile are placed on the top side and left side only * Top-left (Tl): the pins of a tile are placed on the top side and left side only