From 1fb39f803b72e07ceb961272e8442fca1e8148c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Jan 2023 19:52:58 -0800 Subject: [PATCH] [doc] updated vpr arch naming rules --- openfpga_flow/vpr_arch/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 479a359cc..ec4e6fd10 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture +- localClkGen: The clock signal of CLB can be generated by internal programmable resources - : The technology node which the delay numbers are extracted from. - TileOrgz: How tile is organized. * Top-left (Tl): the pins of a tile are placed on the top side and left side only