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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization

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tangxifan 2020-11-02 18:35:26 -07:00
parent e4d974c5c8
commit 1e47203c7c
1 changed files with 0 additions and 3 deletions
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3
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
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@ -464,9 +464,6 @@ void print_verilog_gate_module(const ModuleManager& module_manager,
/* Print timing info */ /* Print timing info */
print_verilog_submodule_timing(fp, circuit_lib, circuit_model); print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Print signal initialization */
print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */ /* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
} }