From 1e47203c7cbafb790f89d71adbcb080b37f5a188 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 2 Nov 2020 18:35:26 -0700 Subject: [PATCH] [Tool] Auto-generated gate Verilog netlist should not contain any signal initalization --- openfpga/src/fpga_verilog/verilog_essential_gates.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index ca3d38734..3fbcb5d45 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -464,9 +464,6 @@ void print_verilog_gate_module(const ModuleManager& module_manager, /* Print timing info */ print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - /* Put an end to the Verilog module */ print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); }