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Corrections of some syntax errors

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Baudouin Chauviere 2018-10-09 14:46:43 -06:00
parent 8565e4e376
commit 1e04436cbb
1 changed files with 17 additions and 9 deletions
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examples/Examples_README.md
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@ -6,13 +6,14 @@ The goal of this example is just to make a first step into the software. The .bl
The .xml is currently on <layout auto="1.0"/> which means that the size depends on the .blif. Since the .blif is The .xml is currently on <layout auto="1.0"/> which means that the size depends on the .blif. Since the .blif is
almost empty, only 1 CLB will be generated. almost empty, only 1 CLB will be generated.
![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_1.png "Example_1_FPGA") ![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA")
Schematic of the FPGA generated during example_1.
Schematic of the FPGA generated during example_1.
The CLB integrates a 4-inputs LUT, a FF and a MUX. The CLB integrates a 4-inputs LUT, a FF and a MUX.
###**Things to understand in this example** ---
**Things to understand in this example**
Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures. Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures.
@ -24,13 +25,15 @@ Everything won't be explained in detail but few important structures (some commo
<spice_settings> <spice_settings>
... all tech and spice parameters are defined here. ... all tech and spice parameters are defined here.
<module_spice_models> <module_spice_models>
... define the Basic Elements of the architecture and the modules that cannot be generated (i.e. the Flip-Flop) but need to be called. ... define the Basic Elements of the architecture and the modules that cannot
be generated (i.e. the Flip-Flop) but need to be called.
</module_spice_models> </module_spice_models>
</spice_settings> </spice_settings>
<cblocks> <cblocks>
... complex blocks ... complex blocks
<complexblocklist> <complexblocklist>
... here we define the hierarchy of the primitive blocks and interconnect them together ... here we define the hierarchy of the primitive blocks and interconnect them
together
<pb_type> <pb_type>
... defines the primitive block ... defines the primitive block
</pb_type> </pb_type>
@ -49,14 +52,19 @@ Example_2's goal is to introduce the slices, the interconnections which can be g
In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry. In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
There is a feedbeck-loop from the output of the slices to the input MUXs There is a feedbeck-loop from the output of the slices to the input MUXs
![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_2_the_CLB_.png "Example_2_CLB") ![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB")
Schematic showing the CLB generated in this example.
---
**Things to understand in this example**
###**Things to understand in this example**
```xml ```xml
<layout width="3" height="3"/> <!-- Manual mode of the layout allowing us to choose the number of CLBs --> <layout width="3" height="3"/> <!-- Manual mode of the layout allowing us to choose the number of CLBs -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level"> <!-- Defines how we apply the feedback on the inputs of the slices --> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level">
<!-- Defines how we apply the feedback on the inputs of the slices -->
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[3:0].in" /> <delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[3:0].in" />
<delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" /> <delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
</complete> </complete>