From 1e04436cbbb36b37b70c02ebb4fdf90af94d6dde Mon Sep 17 00:00:00 2001
From: Baudouin Chauviere <baudouin.chauviere@utah.edu>
Date: Tue, 9 Oct 2018 14:46:43 -0600
Subject: [PATCH] Corrections of some syntax errors

---
 examples/Examples_README.md | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/examples/Examples_README.md b/examples/Examples_README.md
index 63ac1b861..1c11126bb 100644
--- a/examples/Examples_README.md
+++ b/examples/Examples_README.md
@@ -6,13 +6,14 @@ The goal of this example is just to make a first step into the software. The .bl
 The .xml is currently on <layout auto="1.0"/> which means that the size depends on the .blif. Since the .blif is 
 almost empty, only 1 CLB will be generated. 
 
-![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_1.png "Example_1_FPGA")
-
-   Schematic of the FPGA generated during example_1.
+![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA")
 
+Schematic of the FPGA generated during example_1.
 The CLB integrates a 4-inputs LUT, a FF and a MUX. 
 
-###**Things to understand in this example**
+---
+
+**Things to understand in this example**
 
 Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures.
 
@@ -24,13 +25,15 @@ Everything won't be explained in detail but few important structures (some commo
 	<spice_settings>
 		... all tech and spice parameters are defined here.
 		<module_spice_models>
-			... define the Basic Elements of the architecture and the modules that cannot be generated (i.e. the Flip-Flop) but need to be called.
+			... define the Basic Elements of the architecture and the modules that cannot 
+			be generated (i.e. the Flip-Flop) but need to be called.
 		</module_spice_models>
 	</spice_settings>
 	<cblocks>
 		... complex blocks
 		<complexblocklist>
-			... here we define the hierarchy of the primitive blocks and interconnect them together
+			... here we define the hierarchy of the primitive blocks and interconnect them 
+			together
 			<pb_type>
 				... defines the primitive block
 			</pb_type>
@@ -49,14 +52,19 @@ Example_2's goal is to introduce the slices, the interconnections which can be g
 In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
 There is a feedbeck-loop from the output of the slices to the input MUXs
 
-![alt text](https://github.com/LNIS-Projects/OpenFPGA/tree/master/examplesfigures/example_2_the_CLB_.png "Example_2_CLB")
+![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB")
 
+Schematic showing the CLB generated in this example.
+
+---
+
+**Things to understand in this example**
 
-###**Things to understand in this example**
 ```xml
 <layout width="3" height="3"/> <!-- Manual mode of the layout allowing us to choose the number of CLBs -->
 
-<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level"> <!-- Defines how we apply the feedback on the inputs of the slices -->
+<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level"> 
+	<!-- Defines how we apply the feedback on the inputs of the slices -->
 	<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[3:0].in" />
 	<delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
 </complete>