[Flow] Example of using test variable in task conf
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ganeshgore
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1554f583b7
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1d993296d8
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@ -1,10 +1,11 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N8_40nm.xml
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This annotation supports the k6_N8_40nm.xml
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- General purpose logic block
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- K = 6, N = 8, I = 32
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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TEST_VARIABLE = ${TEST_VARIABLE}
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-->
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<openfpga_architecture>
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<technology_library>
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@ -101,7 +102,8 @@
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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@ -109,7 +111,8 @@
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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@ -140,14 +143,14 @@
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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@ -165,14 +168,14 @@
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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@ -199,9 +202,9 @@
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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@ -0,0 +1 @@
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TEST_VARIABLE: 100
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@ -14,6 +14,7 @@ spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
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