diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
index 74d1d9933..59b00016f 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
@@ -1,10 +1,11 @@
 <!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N8_40nm.xml 
+     This annotation supports the k6_N8_40nm.xml
      - General purpose logic block
        - K = 6, N = 8, I = 32
        - Single mode
      - Routing architecture
        - L = 4, fc_in = 0.15, fc_out = 0.1
+    TEST_VARIABLE = ${TEST_VARIABLE}
   -->
 <openfpga_architecture>
   <technology_library>
@@ -101,7 +102,8 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
     </circuit_model>
     <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
       <design_technology type="cmos"/>
@@ -109,7 +111,8 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
     </circuit_model>
     <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@@ -140,14 +143,14 @@
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
     <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+      <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -165,14 +168,14 @@
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
     <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="output" prefix="Qb" size="1"/>
+      <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
@@ -199,9 +202,9 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
     <!-- End physical pb_type binding in complex block IO -->
 
     <!-- physical pb_type binding in complex block CLB -->
diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/design_variables.yml b/openfpga_flow/tasks/basic_tests/generate_fabric/config/design_variables.yml
new file mode 100644
index 000000000..de1dbf341
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/design_variables.yml
@@ -0,0 +1 @@
+TEST_VARIABLE: 100
\ No newline at end of file
diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
index 9c3fd2442..68cee7380 100644
--- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
@@ -14,6 +14,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
+arch_variable_file=${PATH:TASK_DIR}/design_variables.yml 
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga